Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87C42C636D3 for ; Mon, 6 Feb 2023 20:25:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230254AbjBFUY7 (ORCPT ); Mon, 6 Feb 2023 15:24:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33508 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230364AbjBFUYy (ORCPT ); Mon, 6 Feb 2023 15:24:54 -0500 Received: from mail-ot1-x32b.google.com (mail-ot1-x32b.google.com [IPv6:2607:f8b0:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8886517CFF for ; Mon, 6 Feb 2023 12:24:52 -0800 (PST) Received: by mail-ot1-x32b.google.com with SMTP id 14-20020a9d010e000000b0068bdddfa263so3550900otu.2 for ; Mon, 06 Feb 2023 12:24:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=ii3QWaTSpWqp8nAIBHYKbEzhocMIY28k394B8Gv37po=; b=EIsiXELTDJZsBHSzEz0zei/PUThrVQSlx0895jVSVUXzJ9Ee0VIVViPE29DCHdJQ1I ueoaQxqXV4qHNWNBu6FhGAPMC3i3SsTdk3p9nY7zcUAizG7Zh539bk3rjJFuAQgf02Md wbmyC2j/iNPuVdMqHG0w81geTiflP2FO6+dW+rWN02ZYRuI5dNYXZ2Beh9tTg+cQ/8WW YdfESXCvyBZsWyQjfB+IzEXp15yDOnJvxBaTsuFYjWTVTu8xYibijEZXh2y29ujyQfSa zhVo3saNVNroFTdkrlh+zFCkNITKmkjN1PJ6hl65Vt4RHbE6RDMPKlPrY09T/jeT7Hdh Zc4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ii3QWaTSpWqp8nAIBHYKbEzhocMIY28k394B8Gv37po=; b=KRDZtcMCkM/GJGoZA0vwkhcIAVyI8LaPFHI3LfLEYj8TD4Xdcp2fLi4Rx/wcFI58TV vTHbox/3ABrDwEdLw3QRUiHNq4655VAJdmeZVI0T1xBbkh7adn1QMbZEo0LT8qKFWc/8 7iZAaCIrbyff4nQGk5SpD9XdJge8xtRr6Xw/6krW7Fb5UEGrGV4iPxVBL1lLIa6eFa7n s85srUGcmny6bOJl86gTnkri443AtzefJpE/ESdbofVGnu8vyL+KlSCgJjWRJDbdlBhx bTOmkb1GC33qXjUaeYR/thyLgN8lXUBW1x+lvmQ89+dFl5GnGqF8AyccMPAdcotUcEOz ysXQ== X-Gm-Message-State: AO0yUKUTAt0Noo2WXjgy6S1x8nso7ZD+/6UrM5u7qRJpOPhM4OK5YkeI f9YhHzDzouFtNBgfYtDRJas3bpwXnZ0sUvO2k4I= X-Google-Smtp-Source: AK7set9oYVPJvXFFlrdhnRzD5XmmpUtCk86aL0C9pwbKJGoLMv/n+wmWY4auI9t864Gv+GlUtukuDRtHa2bkjtuBMD4= X-Received: by 2002:a05:6830:22e1:b0:686:413a:59ae with SMTP id t1-20020a05683022e100b00686413a59aemr40628otc.120.1675715091814; Mon, 06 Feb 2023 12:24:51 -0800 (PST) MIME-Version: 1.0 References: <20230206193620.69550-1-arnd@kernel.org> In-Reply-To: <20230206193620.69550-1-arnd@kernel.org> From: Alex Deucher Date: Mon, 6 Feb 2023 15:24:39 -0500 Message-ID: Subject: Re: [PATCH] [SUBMITTED 20210927] [RESEND^2] drm/amdgpu: fix enum odm_combine_mode mismatch To: Arnd Bergmann Cc: Harry Wentland , Leo Li , Rodrigo Siqueira , Aric Cyr , Arnd Bergmann , "Pan, Xinhui" , linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, Dmytro Laktyushkin , Nevenko Stupar , dri-devel@lists.freedesktop.org, Daniel Vetter , Alex Deucher , Yang Li , Jun Lei , David Airlie , =?UTF-8?Q?Christian_K=C3=B6nig?= , Pavle Kotarac Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Feb 6, 2023 at 2:36 PM Arnd Bergmann wrote: > > From: Arnd Bergmann > > A conversion from 'bool' to 'enum odm_combine_mode' was incomplete, > and gcc warns about this with many instances of > > display/dc/dml/dcn20/display_mode_vba_20.c:3899:44: warning: implicit conversion from 'enum ' to 'enum > odm_combine_mode' [-Wenum-conversion] > 3899 | locals->ODMCombineEnablePerState[i][k] = false; > > Change the ones that we get a warning for, using the same numerical > values to leave the behavior unchanged. > > Fixes: 5fc11598166d ("drm/amd/display: expand dml structs") > Link: https://lore.kernel.org/all/20201026210039.3884312-3-arnd@kernel.org/ > Link: https://lore.kernel.org/all/20210927100659.1431744-1-arnd@kernel.org/ > Signed-off-by: Arnd Bergmann > --- > I sent this in 2020 and in 2021, but never got a reply and the warning > is still there. Applied. Sorry for the delay. Alex > --- > .../amd/display/dc/dml/dcn20/display_mode_vba_20.c | 8 ++++---- > .../amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 10 +++++----- > .../amd/display/dc/dml/dcn21/display_mode_vba_21.c | 12 ++++++------ > 3 files changed, 15 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c > index f34bc3c8da41..69c41e3e3ba2 100644 > --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c > +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c > @@ -3901,14 +3901,14 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l > mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2 > * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); > > - locals->ODMCombineEnablePerState[i][k] = false; > + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled; > mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine; > if (mode_lib->vba.ODMCapability) { > if (locals->PlaneRequiredDISPCLKWithoutODMCombine > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) { > - locals->ODMCombineEnablePerState[i][k] = true; > + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; > mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine; > } else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) { > - locals->ODMCombineEnablePerState[i][k] = true; > + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; > mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine; > } > } > @@ -3961,7 +3961,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l > locals->RequiredDISPCLK[i][j] = 0.0; > locals->DISPCLK_DPPCLK_Support[i][j] = true; > for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { > - locals->ODMCombineEnablePerState[i][k] = false; > + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled; > if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) { > locals->NoOfDPP[i][j][k] = 1; > locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k] > diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c > index 366138df0fe2..f475a0ae946c 100644 > --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c > +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c > @@ -4012,17 +4012,17 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode > mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2 > * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); > > - locals->ODMCombineEnablePerState[i][k] = false; > + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled; > mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine; > if (mode_lib->vba.ODMCapability) { > if (locals->PlaneRequiredDISPCLKWithoutODMCombine > MaxMaxDispclkRoundedDown) { > - locals->ODMCombineEnablePerState[i][k] = true; > + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; > mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine; > } else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN20_MAX_DSC_IMAGE_WIDTH)) { > - locals->ODMCombineEnablePerState[i][k] = true; > + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; > mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine; > } else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) { > - locals->ODMCombineEnablePerState[i][k] = true; > + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; > mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine; > } > } > @@ -4075,7 +4075,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode > locals->RequiredDISPCLK[i][j] = 0.0; > locals->DISPCLK_DPPCLK_Support[i][j] = true; > for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { > - locals->ODMCombineEnablePerState[i][k] = false; > + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled; > if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) { > locals->NoOfDPP[i][j][k] = 1; > locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k] > diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c > index eeb4d3441e1d..3a896d0172a9 100644 > --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c > +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c > @@ -4106,17 +4106,17 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l > mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2 > * (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); > > - locals->ODMCombineEnablePerState[i][k] = false; > + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled; > mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine; > if (mode_lib->vba.ODMCapability) { > if (locals->PlaneRequiredDISPCLKWithoutODMCombine > MaxMaxDispclkRoundedDown) { > - locals->ODMCombineEnablePerState[i][k] = true; > + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; > mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine; > } else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN21_MAX_DSC_IMAGE_WIDTH)) { > - locals->ODMCombineEnablePerState[i][k] = true; > + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; > mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine; > } else if (locals->HActive[k] > DCN21_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) { > - locals->ODMCombineEnablePerState[i][k] = true; > + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1; > mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine; > } > } > @@ -4169,7 +4169,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l > locals->RequiredDISPCLK[i][j] = 0.0; > locals->DISPCLK_DPPCLK_Support[i][j] = true; > for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { > - locals->ODMCombineEnablePerState[i][k] = false; > + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled; > if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) { > locals->NoOfDPP[i][j][k] = 1; > locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k] > @@ -5234,7 +5234,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l > mode_lib->vba.ODMCombineEnabled[k] = > locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k]; > } else { > - mode_lib->vba.ODMCombineEnabled[k] = false; > + mode_lib->vba.ODMCombineEnabled[k] = dm_odm_combine_mode_disabled; > } > mode_lib->vba.DSCEnabled[k] = > locals->RequiresDSC[mode_lib->vba.VoltageLevel][k]; > -- > 2.39.0 >