Date:   Tue, 7 Feb 2023 08:48:56 +0100
From:   Horatiu Vultur <horatiu.vultur@microchip.com>
To:     Andy Shevchenko <andy.shevchenko@gmail.com>
CC:     <linux-gpio@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linus.walleij@linaro.org>, <alexandre.belloni@bootlin.com>
Subject: Re: [PATCH] pinctrl: ocelot: Fix alt mode for ocelot
Message-ID: <20230207074856.2akoi4v65cbolinb@soft-dev3-1>
References: <20230206203720.1177718-1-horatiu.vultur@microchip.com>
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The 02/06/2023 22:59, Andy Shevchenko wrote:

Hi Andy,

> 
> On Mon, Feb 6, 2023 at 10:37 PM Horatiu Vultur
> <horatiu.vultur@microchip.com> wrote:
> >
> > In case the driver was trying to set an alternate mode for gpio
> > 0 or 32 then the mode was not set correctly. The reason is that
> > there is computation error inside the function ocelot_pinmux_set_mux
> > because in this case it was trying to shift to left by -1.
> > Fix this by actually shifting the function bits and not the position.
> >
> > Fixes: 4b36082e2e09 ("pinctrl: ocelot: fix pinmuxing for pins after 31")
> > Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
> 
> ...
> 
> >         regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
> >                            BIT(p), f << p);
> >         regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
> > -                          BIT(p), f << (p - 1));
> > +                          BIT(p), (f >> 1) << p);
> 
> I'm not sure I understand how this doesn't break anything that has a
> bit 0 set in f. Is it not a problem?

I don't think it is a problem. This is similar to the implementation of
'lan966x_pinmux_set_mux', the only difference is that
lan966x_pinmux_set_mux has more GPIOs than ocelot.

If we take an example where f equals 0x1 and p equals 0.
REG_ALT(0): BIT(0) & (0x1 << 0) equals 0x1
REG_ALT(1): BIT(0) & ((0x1 >> 1) << 0)) equals 0x0.

Or am I misunderstood something?

> 
> --
> With Best Regards,
> Andy Shevchenko

-- 
/Horatiu