Message-ID: <93d95309-84eb-16c6-b64e-b0c43d784900@collabora.com>
Date:   Tue, 7 Feb 2023 09:45:44 +0100
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Subject: Re: [PATCH v1 05/45] clk: mediatek: mt2712: Migrate topckgen/mcucfg
 to mtk_clk_simple_probe()
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To:     Chen-Yu Tsai <wenst@chromium.org>
Cc:     mturquette@baylibre.com, sboyd@kernel.org, matthias.bgg@gmail.com,
        johnson.wang@mediatek.com, miles.chen@mediatek.com,
        chun-jie.chen@mediatek.com, daniel@makrotopia.org,
        fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com,
        rex-bc.chen@mediatek.com, zhaojh329@gmail.com,
        sam.shih@mediatek.com, edward-jw.yang@mediatek.com,
        yangyingliang@huawei.com, granquet@baylibre.com,
        pablo.sun@mediatek.com, sean.wang@mediatek.com,
        chen.zhong@mediatek.com, linux-kernel@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org
References: <20230206152928.918562-1-angelogioacchino.delregno@collabora.com>
 <20230206152928.918562-6-angelogioacchino.delregno@collabora.com>
 <CAGXv+5Gg60-4B29V9cYUw7b1OVcZvU+w9qdiiBbt10LJsAJiCA@mail.gmail.com>
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
In-Reply-To: <CAGXv+5Gg60-4B29V9cYUw7b1OVcZvU+w9qdiiBbt10LJsAJiCA@mail.gmail.com>
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Il 07/02/23 07:15, Chen-Yu Tsai ha scritto:
> On Mon, Feb 6, 2023 at 11:29 PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> Now that the common mtk_clk_simple_{probe,remove}() functions can deal
>> with divider clocks it is possible to migrate more clock drivers to it:
>> in this case, it's about topckgen.
>> While at it, also perform a fast migration for mcucfg.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> 
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
> 
>> ---
>>   drivers/clk/mediatek/clk-mt2712.c | 127 +++++-------------------------
>>   1 file changed, 21 insertions(+), 106 deletions(-)
>>

..snip..
                      __func__, r);
>> +static const struct mtk_clk_desc topck_desc = {
>> +       .clks = top_clks,
>> +       .num_clks = ARRAY_SIZE(top_clks),
>> +       .fixed_clks = top_fixed_clks,
>> +       .num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
>> +       .factor_clks = top_divs,
>> +       .num_factor_clks = ARRAY_SIZE(top_divs),
>> +       .composite_clks = top_muxes,
>> +       .num_composite_clks = ARRAY_SIZE(top_muxes),
>> +       .divider_clks = top_adj_divs,
>> +       .num_divider_clks = ARRAY_SIZE(top_adj_divs),
>> +       .clk_lock = &mt2712_clk_lock,
> 
> At some point maybe we should look into splitting up the locks to one
> per block, or converting everything to regmap.
> 

I was thinking the same about the locks... but about regmap, that would
actually add up some overhead at every R/W operation and I would really
like to measure that precisely before doing any kind of regmap conversion
for the MediaTek clocks.

Perhaps I'll even find a way to avoid any kind of (even if small) overhead
while doing that sometime in the future, which wouldn't be benefitting only
MediaTek, but also other users like Qualcomm (as they have practically all
clocks on regmap!).

Cheers,
Angelo