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Wed, 8 Feb 2023 05:34:18 GMT Received: from poovendh-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 7 Feb 2023 21:34:08 -0800 From: Poovendhan Selvaraj To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V3 2/5] arm64: dts: qcom: Add support for Crashdump collection on IPQ9574 Date: Wed, 8 Feb 2023 11:03:29 +0530 Message-ID: <20230208053332.16537-3-quic_poovendh@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230208053332.16537-1-quic_poovendh@quicinc.com> References: <20230208053332.16537-1-quic_poovendh@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: e25zmSI0xaXS-KRiKZ2L0E3pPGXTMAwc X-Proofpoint-GUID: e25zmSI0xaXS-KRiKZ2L0E3pPGXTMAwc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-08_02,2023-02-06_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 impostorscore=0 mlxscore=0 phishscore=0 clxscore=1015 mlxlogscore=824 suspectscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302080049 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable Crashdump collection in ipq9574 Co-developed-by: Anusha Rao Signed-off-by: Anusha Rao Co-developed-by: Kathiravan Thirumoorthy Signed-off-by: Kathiravan Thirumoorthy Signed-off-by: Poovendhan Selvaraj --- Changes in V3: - No changes arch/arm64/boot/dts/qcom/ipq9574.dtsi | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 2b86ba17bb32..9c4523f50a57 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -81,6 +81,13 @@ reg = <0x0 0x40000000 0x0 0x0>; }; + firmware { + scm { + compatible = "qcom,scm-ipq9574", "qcom,scm"; + qcom,dload-mode = <&tcsr_boot_misc 0>; + }; + }; + pmu { compatible = "arm,cortex-a73-pmu"; interrupts = ; @@ -95,11 +102,17 @@ #address-cells = <2>; #size-cells = <2>; ranges; - tz_region: tz@4a600000 { reg = <0x0 0x4a600000 0x0 0x400000>; no-map; }; + + smem@4aa00000 { + compatible = "qcom,smem"; + reg = <0x0 0x4aa00000 0x0 0x00100000>; + hwlocks = <&tcsr_mutex 0>; + no-map; + }; }; soc: soc@0 { @@ -150,6 +163,17 @@ #power-domain-cells = <1>; }; + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x8000>; + #hwlock-cells = <1>; + }; + + tcsr_boot_misc: syscon@193d100 { + ompatible = "qcom,tcsr-ipq9574", "syscon"; + reg = <0x0193d100 0x4>; + }; + sdhc_1: mmc@7804000 { compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, <0x07805000 0x1000>; -- 2.17.1