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Wed, 8 Feb 2023 03:17:01 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , , , , , , , , Manikanta Maddireddy Subject: [RFC,v14 0/5] Add DT based PCIe wake support in PCI core driver Date: Wed, 8 Feb 2023 16:46:40 +0530 Message-ID: <20230208111645.3863534-1-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT034:EE_|CH0PR12MB5092:EE_ X-MS-Office365-Filtering-Correlation-Id: 5bdfcf60-d439-4a7d-7d9c-08db09c60969 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nmDKyr4MU4mczo2vY8Oy/qv/V0PtmyeEiiF6b9yFl2zlVlL4fg0CWKbYQefJ+iM8jt03kY3N0DOWJQI6EFtSyQ54rvcTjFaTxWIOJJzGdIurJSqgNFbhmMEJ637MlOCMK4TdHb8k2H6cYCMH5NIa1raPeg4ONFFAHQWXAOnJZHKIcdMPkKMRODCPwnZyLFhdj8cKrWzcjpjOwWnZp3tqqXpPsZNAqwr+B7iErCwyB9eGD3MZRMK9UHf4h+s3qJZAcA90yM2Cp49jxr1qnqxMET4TPUnzRfnmAl7boktjC770/evXvdwx3YEyV33/0PKA7B2/4iNBCqTIs6SYDtDJZr6sNsXUzfcZgca157BR8lFttgxJp2Gv+ANV91fpCJvWdHKgzO2pUByGxUkS4bSmWMSI82a1iAxdfTWXKidhP/OFxeIWx/SabD4lFxYhxMMaPO/k1jwhl2EiAStW8yp/i82jKeV34kYiZ01IKrAmx3WdULuSJGsAAcJy0TXuowDFrfNW1WEEVxjfy9t/xG6vM2wEedZhZV13qNKMCC2LFzEMh/bOZqkQixCdfp5SkRwz2AiKeH7WKEmHhKQANFNL/BJAmSgGyAbjo7fZ8gB6GLpSIdS5nVh+d4tfjE+m1rTx2KLxhaL71JCAtDqbkPSP34A1peSVR34X9yQje5g18mNEttRN1lz/Q+FFYc4/K1kQ/Z4lmmmKF7zakOGQivtPOD1dvclAM34SmgfpiqBXxO+C1UsYLQCC6IWzEVu0AsyP/CtFgBgK/7wBOh6Rczaqx2EgfIca6sYeGm9GO86wDSQ= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(376002)(396003)(346002)(39860400002)(136003)(451199018)(46966006)(40470700004)(36840700001)(8936002)(2906002)(41300700001)(7416002)(70586007)(8676002)(70206006)(4326008)(86362001)(316002)(54906003)(110136005)(356005)(7636003)(7696005)(5660300002)(82740400003)(40460700003)(478600001)(83380400001)(6666004)(1076003)(107886003)(36756003)(26005)(2616005)(186003)(82310400005)(36860700001)(40480700001)(966005)(336012)(426003)(47076005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 11:17:16.8202 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5bdfcf60-d439-4a7d-7d9c-08db09c60969 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5092 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Below series [1] attempted to support DT based PCIe wake feature in generic PCI core driver. This series was left at v13 and final comments are not addressed. I am continuing this series from v14 by addressing all comments in v13. I dropped rockchip device tree patch because I don't have hardware to verify it. Instead, I verified these patches on NVIDIA Jetson AGX Orin Developer Kit and included its device tree changes in this series. [1] https://lore.kernel.org/all/20171226023646.17722-1-jeffy.chen@rock-chips.com/ Changes in v14: Updated commit message for DT bindings patch to reflect that DT properties are tied to PCI-PCI Bridge. Addressed review comments on PCI interrupt parsing patch. Dropped rockchip device tree patch. Added Jetson AGX OrinDeveloper Kit device tree and Tegra PMC patches. Changes in v13: Fix compiler error reported by kbuild test robot Changes in v12: Only add irq definitions for PCI devices and rewrite the commit message. Enable the wake irq in noirq stage to avoid possible irq storm. Changes in v11: Address Brian's comments. Only support 1-per-device PCIe WAKE# pin as suggested. Move to pcie port as Brian suggested. Changes in v10: Use device_set_wakeup_capable() instead of device_set_wakeup_enable(), since dedicated wakeirq will be lost in device_set_wakeup_enable(false). Changes in v9: Add section for PCI devices and rewrite the commit message. Fix check error in .cleanup(). Move dedicated wakeirq setup to setup() callback and use device_set_wakeup_enable() to enable/disable. Rewrite the commit message. Changes in v8: Add optional "pci", and rewrite commit message. Add pci-of.c and use platform_pm_ops to handle the PCIe WAKE# signal. Rewrite the commit message. Changes in v7: Move PCIE_WAKE handling into pci core. Changes in v6: Fix device_init_wake error handling, and add some comments. Changes in v5: Move to pci.txt Rebase. Use "wakeup" instead of "wake" Changes in v3: Fix error handling. Changes in v2: Use dev_pm_set_dedicated_wake_irq. Jeffy Chen (3): dt-bindings: PCI: Add definition of PCIe WAKE# irq and PCI irq of/irq: Adjust of_pci_irq parsing for multiple interrupts PCI / PM: Add support for the PCIe WAKE# signal for OF Manikanta Maddireddy (2): arm64: tegra: Add PCIe port node with PCIe WAKE# for C1 controller soc/tegra: pmc: Add Tegra234 PCIe wake event Documentation/devicetree/bindings/pci/pci.txt | 8 +++ .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 11 ++++ drivers/pci/of.c | 63 ++++++++++++++++++- drivers/pci/pci-driver.c | 10 +++ drivers/pci/pci.c | 7 +++ drivers/pci/pci.h | 8 +++ drivers/soc/tegra/pmc.c | 1 + 7 files changed, 105 insertions(+), 3 deletions(-) -- 2.25.1