Date:   Wed, 8 Feb 2023 17:14:04 +0100
From:   Thierry Reding <thierry.reding@gmail.com>
To:     Manikanta Maddireddy <mmaddireddy@nvidia.com>
Cc:     bhelgaas@google.com, petlozup@nvidia.com,
        rafael.j.wysocki@intel.com, lpieralisi@kernel.org, robh@kernel.org,
        jeffy.chen@rock-chips.com, krzysztof.kozlowski+dt@linaro.org,
        jonathanh@nvidia.com, dmitry.osipenko@collabora.com,
        viresh.kumar@linaro.org, gregkh@linuxfoundation.org,
        steven.price@arm.com, kw@linux.com, linux-pci@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org,
        vidyas@nvidia.com
Subject: Re: [RFC,v14 4/5] arm64: tegra: Add PCIe port node with PCIe WAKE#
 for C1 controller
Message-ID: <Y+PKTNEAuPHBdwqX@orome>
References: <20230208111645.3863534-1-mmaddireddy@nvidia.com>
 <20230208111645.3863534-5-mmaddireddy@nvidia.com>
 <Y+OJaGY6mcxM0JOF@orome>
 <1b24e9f5-539a-dd0f-6485-5dbf3757ef27@nvidia.com>
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On Wed, Feb 08, 2023 at 05:43:35PM +0530, Manikanta Maddireddy wrote:
>=20
> On 2/8/2023 5:07 PM, Thierry Reding wrote:
> > On Wed, Feb 08, 2023 at 04:46:44PM +0530, Manikanta Maddireddy wrote:
> > > Add PCIe port node under the PCIe controller-1 device tree node to su=
pport
> > > PCIe WAKE# interrupt for WiFi.
> > >=20
> > > Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> > > ---
> > >=20
> > > Changes in v14:
> > > New patch in the series to support PCIe WAKE# in NVIDIA Jetson AGX Or=
in.
> > >=20
> > >   .../dts/nvidia/tegra234-p3737-0000+p3701-0000.dts     | 11 ++++++++=
+++
> > >   1 file changed, 11 insertions(+)
> > >=20
> > > diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-000=
0.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
> > > index 8a9747855d6b..9c89be263141 100644
> > > --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
> > > +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
> > > @@ -2147,6 +2147,17 @@ pcie@14100000 {
> > >   			phys =3D <&p2u_hsio_3>;
> > >   			phy-names =3D "p2u-0";
> > > +
> > > +			pci@0,0 {
> > > +				reg =3D <0x0000 0 0 0 0>;
> > > +				#address-cells =3D <3>;
> > > +				#size-cells =3D <2>;
> > > +				ranges;
> > > +
> > > +				interrupt-parent =3D <&gpio>;
> > > +				interrupts =3D <TEGRA234_MAIN_GPIO(L, 2) IRQ_TYPE_LEVEL_LOW>;
> > > +				interrupt-names =3D "wakeup";
> > > +			};
> > Don't we need to wire this to the PMC interrupt controller and the wake
> > event corresponding to the L2 GPIO? Otherwise none of the wake logic in
> > PMC will get invoked.
> >=20
> > Thierry
> PCIe wake is gpio based not pmc, only wake support is provided by PMC
> controller.
> I verified this patch and able to wake up Tegra from suspend.
> Petlozu, correct me if my understanding is wrong.

The way that this usually works is that you need to use something like
this:

	interrupt-parent =3D <&pmc>;
	interrupts =3D <1 IRQ_TYPE_LEVEL_LOW>;
	interrupt-names =3D "wakeup";

This will then cause the PMC's interrupt chip callbacks to setup all the
wake-related interrupts and use the internal wake event tables to
forward the GPIO/IRQ corresponding to the PMC wake event to the GPIO
controller or GIC, respectively.

If you use &gpio as the interrupt parent, none of the PMC logic will be
invoked, so unless this is somehow set up correctly by default, the PMC
wouldn't be able to wake up the system.

Thierry

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