Date:   Wed, 08 Feb 2023 23:20:10 +0000
From:   Conor Dooley <conor@kernel.org>
To:     Heiko Stuebner <heiko@sntech.de>, palmer@rivosinc.com
CC:     linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
        christoph.muellner@vrull.eu, ajones@ventanamicro.com,
        Heiko Stuebner <heiko.stuebner@vrull.eu>
Subject: Re: [PATCH 1/2] RISC-V: fix ordering of Zbb extension
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Hey Heiko,

On 8 February 2023 22:53:27 GMT, Heiko Stuebner <heiko@sntech=2Ede> wrote:
>From: Heiko Stuebner <heiko=2Estuebner@vrull=2Eeu>
>
>As Andrew reported,
>    Zb* comes after Zi* according 27=2E11 "Subset Naming Convention"
>so fix the ordering accordingly=2E
>
>Reported-by: Andrew Jones <ajones@ventanamicro=2Ecom>
>Signed-off-by: Heiko Stuebner <heiko=2Estuebner@vrull=2Eeu>

The whole "getting it wrong immediately after fixing it up" ;)

Reviewed-by: Conor Dooley <conor=2Edooley@microchip=2Ecom>

>---
> arch/riscv/kernel/cpu=2Ec | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/arch/riscv/kernel/cpu=2Ec b/arch/riscv/kernel/cpu=2Ec
>index 420228e219f7=2E=2E8400f0cc9704 100644
>--- a/arch/riscv/kernel/cpu=2Ec
>+++ b/arch/riscv/kernel/cpu=2Ec
>@@ -185,9 +185,9 @@ arch_initcall(riscv_cpuinfo_init);
>  * New entries to this struct should follow the ordering rules described=
 above=2E
>  */
> static struct riscv_isa_ext_data isa_ext_arr[] =3D {
>-	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
> 	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
> 	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
>+	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
> 	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
> 	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
> 	__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),