Date:   Thu, 9 Feb 2023 09:47:25 +0100
From:   =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= <clement.leger@bootlin.com>
To:     Vladimir Oltean <olteanv@gmail.com>
Cc:     Andrew Lunn <andrew@lunn.ch>,
        Florian Fainelli <f.fainelli@gmail.com>,
        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
        Herve Codina <herve.codina@bootlin.com>,
        =?UTF-8?B?TWlxdcOobA==?= Raynal <miquel.raynal@bootlin.com>,
        Milan Stevanovic <milan.stevanovic@se.com>,
        Jimmy Lalande <jimmy.lalande@se.com>,
        Pascal Eberhard <pascal.eberhard@se.com>,
        Arun Ramadoss <Arun.Ramadoss@microchip.com>,
        linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH net-next v3 3/3] net: dsa: rzn1-a5psw: add vlan support
Message-ID: <20230209094725.3ac772ff@fixe.home>
In-Reply-To: <20230208220309.4ekk4xpmpx27rkt6@skbuf>
References: <20230208161749.331965-1-clement.leger@bootlin.com>
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        <20230208161749.331965-4-clement.leger@bootlin.com>
        <20230208161749.331965-4-clement.leger@bootlin.com>
        <20230208220309.4ekk4xpmpx27rkt6@skbuf>
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Le Thu, 9 Feb 2023 00:03:09 +0200,
Vladimir Oltean <olteanv@gmail.com> a =C3=A9crit :

> On Wed, Feb 08, 2023 at 05:17:49PM +0100, Cl=C3=A9ment L=C3=A9ger wrote:
> > +static void a5psw_port_vlan_tagged_cfg(struct a5psw *a5psw, int vlan_r=
es_id,
> > +				       int port, bool set)
> > +{
> > +	u32 mask =3D A5PSW_VLAN_RES_WR_PORTMASK | A5PSW_VLAN_RES_RD_TAGMASK |
> > +		   BIT(port);
> > +	u32 vlan_res_off =3D A5PSW_VLAN_RES(vlan_res_id);
> > +	u32 val =3D A5PSW_VLAN_RES_WR_TAGMASK, reg;
> > +
> > +	if (set)
> > +		val |=3D BIT(port);
> > +
> > +	/* Toggle tag mask read */
> > +	a5psw_reg_writel(a5psw, vlan_res_off, A5PSW_VLAN_RES_RD_TAGMASK);
> > +	reg =3D a5psw_reg_readl(a5psw, vlan_res_off);
> > +	a5psw_reg_writel(a5psw, vlan_res_off, A5PSW_VLAN_RES_RD_TAGMASK); =20
>=20
> Is it intentional that this register is written twice?

Yes, the A5PSW_VLAN_RES_RD_TAGMASK bit is a toggle-bit (toggled
by writing a 1 in it) and it allows to read the tagmask (for
vlan tagging) instead of the portmask (for vlan membership):

"""
b28 read_tagmask:

Select contents of mask bits (4:0) when reading the
register. If this bit is set during a write into the register, all
other bits of the write are ignored (i.e. 30,29,16:0) and the bit 28 of
the register toggles (1-> 0; 0-> 1). This is used only to allow
changing the bit 28 without changing any table contents.
"""

>=20
> > +
> > +	reg &=3D ~mask;
> > +	reg |=3D val;
> > +	a5psw_reg_writel(a5psw, vlan_res_off, reg);
> > +} =20


--=20
Cl=C3=A9ment L=C3=A9ger,
Embedded Linux and Kernel engineer at Bootlin
https://bootlin.com