Message-ID: <77bd4509-bd8b-3bcc-e94a-7593505e27c0@arm.com>
Date:   Thu, 9 Feb 2023 10:31:28 +0000
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Subject: Re: [PATCH v3] coresight: tmc: Don't enable TMC when it's not ready.
To:     Yabin Cui <yabinc@google.com>,
        Mathieu Poirier <mathieu.poirier@linaro.org>,
        Mike Leach <mike.leach@linaro.org>,
        Leo Yan <leo.yan@linaro.org>, James Clark <james.clark@arm.com>
Cc:     coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org
References: <CALJ9ZPNrF-HhUNskr=_MJ1CrnO+0xzSN8pMpER3FMqf5Pd0idg@mail.gmail.com>
 <20230202214633.12584-1-yabinc@google.com>
 <CALJ9ZPPte1Gso7LYA6eAVifZJDgdZP+QPdSKUJEpz=+v2S0cag@mail.gmail.com>
From:   Suzuki K Poulose <suzuki.poulose@arm.com>
In-Reply-To: <CALJ9ZPPte1Gso7LYA6eAVifZJDgdZP+QPdSKUJEpz=+v2S0cag@mail.gmail.com>
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On 09/02/2023 01:08, Yabin Cui wrote:
> Friendly ping?
> 
> On Thu, Feb 2, 2023 at 1:46 PM Yabin Cui <yabinc@google.com> wrote:
>>
>> If TMC ETR is enabled without being ready, in later use we may
>> see AXI bus errors caused by accessing invalid addresses.
>>
>> Signed-off-by: Yabin Cui <yabinc@google.com>
>> ---
>> V1 -> V2: Make change to all TMCs instead of just ETR
>> V2 -> V3: Handle etr enable failure in tmc_read_unprepare_etr

As I mentioned, v2 was queued. Please could you update your changes on 
top of the coresight next branch and resend the patch ?

Suzuki