Date:   Thu, 9 Feb 2023 14:50:06 +0100
From:   =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= <clement.leger@bootlin.com>
To:     Florian Fainelli <f.fainelli@gmail.com>
Cc:     Andrew Lunn <andrew@lunn.ch>, Vladimir Oltean <olteanv@gmail.com>,
        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
        Herve Codina <herve.codina@bootlin.com>,
        =?UTF-8?B?TWlxdcOobA==?= Raynal <miquel.raynal@bootlin.com>,
        Milan Stevanovic <milan.stevanovic@se.com>,
        Jimmy Lalande <jimmy.lalande@se.com>,
        Pascal Eberhard <pascal.eberhard@se.com>,
        Arun Ramadoss <Arun.Ramadoss@microchip.com>,
        linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH net-next v3 3/3] net: dsa: rzn1-a5psw: add vlan support
Message-ID: <20230209145006.2b42f5a3@fixe.home>
In-Reply-To: <317ec9fc-87de-2683-dfd4-30fe94e2efd7@gmail.com>
References: <20230208161749.331965-1-clement.leger@bootlin.com>
        <20230208161749.331965-4-clement.leger@bootlin.com>
        <317ec9fc-87de-2683-dfd4-30fe94e2efd7@gmail.com>
Organization: Bootlin
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: quoted-printable
Precedence: bulk

Le Wed, 8 Feb 2023 09:38:04 -0800,
Florian Fainelli <f.fainelli@gmail.com> a =C3=A9crit :

> > +static void a5psw_vlan_setup(struct a5psw *a5psw, int port)
> > +{
> > +	u32 reg;
> > +
> > +	/* Enable TAG always mode for the port, this is actually controlled
> > +	 * by VLAN_IN_MODE_ENA field which will be used for PVID insertion
> > +	 */
> > +	reg =3D A5PSW_VLAN_IN_MODE_TAG_ALWAYS;
> > +	reg <<=3D A5PSW_VLAN_IN_MODE_PORT_SHIFT(port);
> > +	a5psw_reg_rmw(a5psw, A5PSW_VLAN_IN_MODE, A5PSW_VLAN_IN_MODE_PORT(port=
),
> > +		      reg); =20
>=20
> If we always enable VLAN mode, which VLAN ID do switch ports not part of=
=20
> a VLAN aware bridge get classified into?

As answered on Vladimir question, it is VLAN_IN_MODE_ENAnot always VLAN ena=
bled as
stated by the comment above but only if VLAN_IN_MODE_ENA is set (which
is done when setting a PVID only).

>=20
> > +
> > +	/* Set transparent mode for output frame manipulation, this will depe=
nd
> > +	 * on the VLAN_RES configuration mode
> > +	 */
> > +	reg =3D A5PSW_VLAN_OUT_MODE_TRANSPARENT;
> > +	reg <<=3D A5PSW_VLAN_OUT_MODE_PORT_SHIFT(port);
> > +	a5psw_reg_rmw(a5psw, A5PSW_VLAN_OUT_MODE,
> > +		      A5PSW_VLAN_OUT_MODE_PORT(port), reg); =20
>=20
> Sort of a follow-on to the previous question, what does transparent=20
> mean? Does that mean the frames ingressing with a certain VLAN tag will=20
> egress with the same VLAN tag in the absence of a VLAN configuration=20
> rewriting the tag?

Yes, here is an excerpt of the documentation which should clarified your
question (VLAN Table is actually stored in VLAN_RES registers):

- If frame=E2=80=99s VLAN id is found in the VLAN table (see Section
4.5.3.9(3)(b), VLAN Domain Resolution / VLAN Table) and the port is
defined as tagged for the VLAN, the frame is not modified.

- If frame=E2=80=99s VLAN id is found in the VLAN table and the port is def=
ined
as untagged for the VLAN, the first VLAN tag is removed from the frame.

- If frame=E2=80=99s VLAN id is not found in the VLAN table, the frame is n=
ot
modified.

Thanks,

--=20
Cl=C3=A9ment L=C3=A9ger,
Embedded Linux and Kernel engineer at Bootlin
https://bootlin.com