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From:   Stephen Boyd <swboyd@chromium.org>
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Date:   Thu, 9 Feb 2023 18:02:36 -0500
Message-ID: <CAE-0n51Ov_0p0JW=4M6NsVzoKUBGaZDKAJtm+wHMMLMiNpDE1Q@mail.gmail.com>
Subject: Re: [PATCH v5 5/8] arm64: dts: qcom: sc7280: Update lpass_tlmm node
To:     Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>,
        agross@kernel.org, alsa-devel@alsa-project.org,
        andersson@kernel.org, broonie@kernel.org,
        devicetree@vger.kernel.org, dianders@chromium.org,
        judyhsiao@chromium.org, konrad.dybcio@somainline.org,
        krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org,
        linux-kernel@vger.kernel.org, mka@chromium.org,
        quic_mohs@quicinc.com, quic_rjendra@quicinc.com,
        quic_rohkumar@quicinc.com, robh+dt@kernel.org,
        srinivas.kandagatla@linaro.org, vkoul@kernel.org
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Quoting Srinivasa Rao Mandadapu (2023-02-06 08:16:38)
> Update lpass_tlmm clock properties, as different clock sources
> are required in ADSP enabled platforms.
> Also update LPASS_MCC register region. This is required to avoid
> memory region conflicts due to overlapping lpass_efuse Q6 regmap
> region used in LPASS PIL node.

If efuse is overlapping, why isn't that made into an nvmem device that
can be used or not used depending on the configuration?