Date:   Fri, 10 Feb 2023 11:33:22 +0530
From:   Vinod Koul <vkoul@kernel.org>
To:     Lizhi Hou <lizhi.hou@amd.com>
Cc:     dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org,
        max.zhen@amd.com, sonal.santan@amd.com, larry.liu@amd.com,
        brian.xu@amd.com, tumic@gpxsee.org
Subject: Re: [PATCH V12 XDMA 0/2] xilinx XDMA driver
Message-ID: <Y+XeKt5yPr1nGGaq@matsya>
References: <1674145926-29449-1-git-send-email-lizhi.hou@amd.com>
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On 19-01-23, 08:32, Lizhi Hou wrote:
> Hello,
> 
> This V12 of patch series is to provide the platform driver to support the
> Xilinx XDMA subsystem. The XDMA subsystem is used in conjunction with the
> PCI Express IP block to provide high performance data transfer between host
> memory and the card's DMA subsystem. It also provides up to 16 user
> interrupt wires to user logic that generate interrupts to the host.
> 
>             +-------+       +-------+       +-----------+
>    PCIe     |       |       |       |       |           |
>    Tx/Rx    |       |       |       |  AXI  |           |
>  <=======>  | PCIE  | <===> | XDMA  | <====>| User Logic|
>             |       |       |       |       |           |
>             +-------+       +-------+       +-----------+
> 
> The XDMA has been used for Xilinx Alveo PCIe devices.
> And it is also integrated into Versal ACAP DMA and Bridge Subsystem.
>     https://www.xilinx.com/products/boards-and-kits/alveo.html
>     https://docs.xilinx.com/r/en-US/pg344-pcie-dma-versal/Introduction-to-the-DMA-and-Bridge-Subsystems
> 
> The device driver for any FPGA based PCIe device which leverages XDMA can
> call the standard dmaengine APIs to discover and use the XDMA subsystem
> without duplicating the XDMA driver code in its own driver.

Applied, thanks


ALso, please dont resend the code every few days, that serves no
purpose. It will be reviewed in the queue!

-- 
~Vinod