Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756537AbXIEKgM (ORCPT ); Wed, 5 Sep 2007 06:36:12 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1755893AbXIEKf6 (ORCPT ); Wed, 5 Sep 2007 06:35:58 -0400 Received: from outbound-fra.frontbridge.com ([62.209.45.174]:20820 "EHLO outbound6-fra-R.bigfish.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755868AbXIEKf5 (ORCPT ); Wed, 5 Sep 2007 06:35:57 -0400 X-BigFish: VP X-MS-Exchange-Organization-Antispam-Report: OrigIP: 163.181.251.8;Service: EHS X-Server-Uuid: 8C3DB987-180B-4465-9446-45C15473FD3E Date: Wed, 5 Sep 2007 12:35:25 +0200 From: "Robert Richter" To: "H. Peter Anvin" cc: "Andreas Herrmann" , "Arjan van de Ven" , patches@x86-64.org, linux-kernel@vger.kernel.org Subject: Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona Message-ID: <20070905103525.GA10749@erda.amd.com> References: <20070903081736.288288000@amd.com> <20070903081736.588599000@amd.com> <20070903013157.72c94891@laptopd505.fenrus.org> <20070903091718.GB22144@alberich.amd.com> <20070903043319.7573875b@laptopd505.fenrus.org> <20070903154734.GC22086@alberich.amd.com> <46DE45A2.40403@zytor.com> <20070905084427.GE6409@erda.amd.com> <46DE80F0.4000706@zytor.com> MIME-Version: 1.0 In-Reply-To: <46DE80F0.4000706@zytor.com> User-Agent: Mutt/1.5.13 (2006-08-11) X-OriginalArrivalTime: 05 Sep 2007 10:35:26.0394 (UTC) FILETIME=[78D249A0:01C7EFA8] X-WSS-ID: 6AC059FA0X86610041-03-01 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1134 Lines: 29 On 05.09.07 11:12:00, H. Peter Anvin wrote: > >PCI Devices will not be the same on the bus since PCI read/write > >functions will have different behavior. Without the patches you will > >get an error when accessing ECS with CF8. We need ECS access for > >patches that setups local interrupt vectors. This patches will be > >released soon. > > You're missing the point. How will the PCI bus transactions be > different when using MMCONFIG versus your extended CF8 version? Misunderstood you, with this patch there will be the same behavior, that's the intention. There might be slightly differences in ordering rules for read/write cycles. IO config cycles are serialized while ordering rules for MMIO config cycles may result in unexpected behavior for PCI devices on the bus. -Robert -- Advanced Micro Devices, Inc. Operating System Research Center email: robert.richter@amd.com - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/