Date:   Sat, 11 Feb 2023 12:53:02 +0000
From:   "Russell King (Oracle)" <linux@armlinux.org.uk>
To:     Daniel Golle <daniel@makrotopia.org>
Cc:     netdev@vger.kernel.org, linux-mediatek@lists.infradead.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        Heiner Kallweit <hkallweit1@gmail.com>,
        Lorenzo Bianconi <lorenzo@kernel.org>,
        Mark Lee <Mark-MC.Lee@mediatek.com>,
        John Crispin <john@phrozen.org>, Felix Fietkau <nbd@nbd.name>,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        DENG Qingfang <dqfext@gmail.com>,
        Landen Chao <Landen.Chao@mediatek.com>,
        Sean Wang <sean.wang@mediatek.com>,
        Paolo Abeni <pabeni@redhat.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Eric Dumazet <edumazet@google.com>,
        "David S. Miller" <davem@davemloft.net>,
        Vladimir Oltean <olteanv@gmail.com>,
        Florian Fainelli <f.fainelli@gmail.com>,
        Andrew Lunn <andrew@lunn.ch>,
        Jianhui Zhao <zhaojh329@gmail.com>,
        =?iso-8859-1?Q?Bj=F8rn?= Mork <bjorn@mork.no>
Subject: Re: [PATCH v4 10/12] net: pcs: add driver for MediaTek SGMII PCS
Message-ID: <Y+ePrq4pTLOuTNIc@shell.armlinux.org.uk>
References: <cover.1676071507.git.daniel@makrotopia.org>
 <1df6229f353a093279d707f8841d71b65aec4d90.1676071508.git.daniel@makrotopia.org>
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In-Reply-To: <1df6229f353a093279d707f8841d71b65aec4d90.1676071508.git.daniel@makrotopia.org>
Sender: Russell King (Oracle) <linux@armlinux.org.uk>
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Hi Daniel,

On Fri, Feb 10, 2023 at 11:39:59PM +0000, Daniel Golle wrote:
> +	if (mpcs->interface != interface) {
> +		/* PHYA power down */
> +		regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
> +				   SGMII_PHYA_PWD, SGMII_PHYA_PWD);
> +
> +		/* Reset SGMII PCS state */
> +		regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,
> +				   SGMII_SW_RESET, SGMII_SW_RESET);
> +
> +		if (mpcs->flags & MTK_SGMII_FLAG_PN_SWAP)
> +			regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL,
> +					   SGMII_PN_SWAP_MASK,
> +					   SGMII_PN_SWAP_TX_RX);
> +
> +		if (interface == PHY_INTERFACE_MODE_2500BASEX)
> +			rgc3 = RG_PHY_SPEED_3_125G;
> +		else
> +			rgc3 = 0;
> +
> +		/* Configure the underlying interface speed */
> +		regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
> +				   RG_PHY_SPEED_MASK, rgc3);
> +
> +		/* Setup the link timer and QPHY power up inside SGMIISYS */
> +		link_timer = phylink_get_link_timer_ns(interface);
> +		if (link_timer < 0)
> +			return link_timer;

The change in patch 7 needs to be propagated to this patch (moving this
to the beginning of this block of code.)

Otherwise, LGTM. Thanks.

-- 
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