Date:   Sat, 11 Feb 2023 23:52:29 +0200
From:   Vladimir Oltean <vladimir.oltean@nxp.com>
To:     Andrew Lunn <andrew@lunn.ch>
Cc:     Maxime Chevallier <maxime.chevallier@bootlin.com>,
        davem@davemloft.net, netdev@vger.kernel.org,
        linux-kernel@vger.kernel.org, thomas.petazzoni@bootlin.com,
        Jakub Kicinski <kuba@kernel.org>,
        Eric Dumazet <edumazet@google.com>,
        Paolo Abeni <pabeni@redhat.com>,
        Florian Fainelli <f.fainelli@gmail.com>,
        Heiner Kallweit <hkallweit1@gmail.com>,
        Russell King <linux@armlinux.org.uk>,
        linux-arm-kernel@lists.infradead.org,
        Ioana Ciornei <ioana.ciornei@nxp.com>
Subject: Re: [PATCH net-next] net: pcs: tse: port to pcs-lynx
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On Fri, Feb 10, 2023 at 09:02:39PM +0100, Andrew Lunn wrote:
> I was wondering if the glue could actually be made generic. The kernel
> has a number of reasonably generic MMIO device drivers, which are just
> given an address range and assume a logical mapping.
> 
> Could this be made into a generic MDIO MMIO bus driver, which just
> gets configured with a base address, and maybe a stride between
> registers?

This sounds interesting to me because I also have at least one other
potential use for it. The "nxp,sja1110-base-tx-mdio" driver does basically
just that, except it's SPI instead of MMIO. So if the generic driver was a
platform device driver and it was aware of dev_get_regmap(), it could
get reused.

What I'm not sure of is the spacing between MDIO registers. For the
SJA1110 CBTX PHY, the registers are 32-bit wide (but contain 16-bit
values). So MII_BMCR is at offset 0x0, MII_BMSR at 0x4 etc. I'd imagine
that other MDIO buses might have MII_BMSR at 0x2.