Message-ID: <2b6bc14b-20df-b61e-6464-61ebb11f24f0@linaro.org>
Date:   Sun, 12 Feb 2023 16:49:25 +0000
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Subject: Re: [PATCH v5 2/5] arm64: dts: qcom: Add msm8939 SoC
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To:     Stephan Gerhold <stephan@gerhold.net>
Cc:     agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org,
        djakov@kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org,
        linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, benl@squareup.com,
        shawn.guo@linaro.org, fabien.parent@linaro.org, leo.yan@linaro.org,
        dmitry.baryshkov@linaro.org, Jun Nie <jun.nie@linaro.org>,
        James Willcox <jwillcox@squareup.com>,
        Joseph Gates <jgates@squareup.com>,
        Max Chen <mchen@squareup.com>, Zac Crosby <zac@squareup.com>,
        Vincent Knecht <vincent.knecht@mailoo.org>
References: <20230206012336.2130341-1-bryan.odonoghue@linaro.org>
 <20230206012336.2130341-3-bryan.odonoghue@linaro.org>
 <Y+T5cF4d667RhrJp@gerhold.net>
From:   Bryan O'Donoghue <bryan.odonoghue@linaro.org>
In-Reply-To: <Y+T5cF4d667RhrJp@gerhold.net>
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On 09/02/2023 13:47, Stephan Gerhold wrote:
>> +			frame@b021000 {
>> +				reg = <0x0b021000 0x1000>,
>> +				      <0x0b022000 0x1000>;
>> +				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> +				frame-number = <0>;
>> +			};
> These timer interrupts are still wrong like mentioned in v3:
> https://lore.kernel.org/linux-arm-msm/Y8fC%2FGCHfENQmBNC@gerhold.net/
> 

Hmm.

This is a copy/paste error from 8916 which I guess we never see in our 
production system, since we use LPM to get to do idle

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bod