From:   Hariprasad Kelam <hkelam@marvell.com>
To:     Jakub Kicinski <kuba@kernel.org>
CC:     "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
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        Sunil Kovvuri Goutham <sgoutham@marvell.com>,
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        "hariprasad.netdev@gmail.com" <hariprasad.netdev@gmail.com>
Subject: Re: [net-next Patch V4 0/4] octeontx2-pf: HTB offload support
Thread-Topic: [net-next Patch V4 0/4] octeontx2-pf: HTB offload support
Thread-Index: AQHZP3OCMLhOpRtKPUaeYRHHBQed/g==
Date:   Mon, 13 Feb 2023 06:22:12 +0000
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References: <20230210111051.13654-1-hkelam@marvell.com>
 <20230210163602.08d1ce5f@kernel.org>
In-Reply-To: <20230210163602.08d1ce5f@kernel.org>
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> On Fri, 10 Feb 2023 16:40:47 +0530 Hariprasad Kelam wrote:
> > octeontx2 silicon and CN10K transmit interface consists of five
> > transmit levels starting from MDQ, TL4 to TL1. Once packets are
> > submitted to MDQ, hardware picks all active MDQs using strict
> > priority, and MDQs having the same priority level are chosen using
> > round robin. Each packet will traverse MDQ, TL4 to TL1 levels.
> > Each level contains an array of queues to support scheduling and
> > shaping.
> >
> > As HTB supports classful queuing mechanism by supporting rate and ceil
> > and allow the user to control the absolute bandwidth to particular
> > classes of traffic the same can be achieved by configuring shapers and
> > schedulers on different transmit levels.
>=20
> Please provide or link to some user-facing documentation under
> Documentation/networking/device_drivers/ethernet/marvell/octeon...

ACK, will add in next version.