Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF6DDC6379F for ; Mon, 13 Feb 2023 13:09:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230465AbjBMNJJ (ORCPT ); Mon, 13 Feb 2023 08:09:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230015AbjBMNJH (ORCPT ); Mon, 13 Feb 2023 08:09:07 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B86A19004; Mon, 13 Feb 2023 05:09:03 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id BCBCB24E154; Mon, 13 Feb 2023 21:08:47 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Feb 2023 21:08:47 +0800 Received: from [192.168.125.74] (183.27.97.168) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Feb 2023 21:08:46 +0800 Message-ID: <7152f39a-5220-63a0-3e13-ef165b0ab0c1@starfivetech.com> Date: Mon, 13 Feb 2023 21:08:46 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.7.2 Subject: Re: [PATCH v1 2/3] dma: dw-axi-dmac: Add support for StarFive DMA Content-Language: en-US To: Vinod Koul CC: , , , Eugeniy Paltsev , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Palmer Dabbelt" , Emil Renner Berthing , References: <20230206113811.23133-1-walker.chen@starfivetech.com> <20230206113811.23133-3-walker.chen@starfivetech.com> From: Walker Chen In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [183.27.97.168] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2023/2/10 16:59, Vinod Koul wrote: > On 06-02-23, 19:38, Walker Chen wrote: >> Adding DMA reset operation in device probe, and using different >> registers according to the hardware handshake number. > > subsystem tag is dmaengine: xxx OK, the tag will be changed to dmaengine. > >> >> Signed-off-by: Walker Chen >> --- >> .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 25 ++++++++++++++++--- >> drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 3 +++ >> 2 files changed, 24 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c >> index a183d93bd7e2..3581810033d2 100644 >> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c >> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c >> @@ -25,6 +25,7 @@ >> #include >> #include >> #include >> +#include >> #include >> #include >> >> @@ -86,7 +87,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan, >> >> cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS | >> config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS); >> - if (chan->chip->dw->hdata->reg_map_8_channels) { >> + if (chan->chip->dw->hdata->reg_map_8_channels && >> + !chan->chip->dw->hdata->use_cfg2) { > > what about older/other platforms that dont have use_cfg2? The use_cfg2 variable's default value is false, the original logic will not be affected. Rob herring gave a suggestion that it is assigned according to compatible string, like that: if (of_device_is_compatible(node, "starfive,jh7110-axi-dma")) { ... chip->dw->hdata->use_cfg2 = true; } > >> cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS | >> config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS | >> config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS | >> @@ -541,8 +543,6 @@ static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set) >> (chan->id * DMA_APB_HS_SEL_BIT_SIZE)); >> reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE)); >> lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0); >> - >> - return; >> } >> Thanks Best regards, Walker