Date:   Mon, 13 Feb 2023 10:45:38 -0400
From:   Jason Gunthorpe <jgg@nvidia.com>
To:     "Tian, Kevin" <kevin.tian@intel.com>
Cc:     Alex Williamson <alex.williamson@redhat.com>,
        Nicolin Chen <nicolinc@nvidia.com>,
        "joro@8bytes.org" <joro@8bytes.org>,
        "will@kernel.org" <will@kernel.org>,
        "robin.murphy@arm.com" <robin.murphy@arm.com>,
        "shuah@kernel.org" <shuah@kernel.org>,
        "Liu, Yi L" <yi.l.liu@intel.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "iommu@lists.linux.dev" <iommu@lists.linux.dev>,
        "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
        "linux-kselftest@vger.kernel.org" <linux-kselftest@vger.kernel.org>,
        "baolu.lu@linux.intel.com" <baolu.lu@linux.intel.com>,
        "Raj, Ashok" <ashok.raj@intel.com>
Subject: Re: [PATCH v2 02/10] iommu: Introduce a new
 iommu_group_replace_domain() API
Message-ID: <Y+pNEtgyAJwLjERa@nvidia.com>
References: <cover.1675802050.git.nicolinc@nvidia.com>
 <fa81379dca611c1d9f50f9d8cd2bca0d4ec7f965.1675802050.git.nicolinc@nvidia.com>
 <20230210165110.4e89ce55.alex.williamson@redhat.com>
 <Y+bk+GSCPKOJfr1f@nvidia.com>
 <BL1PR11MB527176BE1F6DFA3D2942664D8CDD9@BL1PR11MB5271.namprd11.prod.outlook.com>
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <BL1PR11MB527176BE1F6DFA3D2942664D8CDD9@BL1PR11MB5271.namprd11.prod.outlook.com>
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?qpnRjDlnKGtx6cDIjkfQXnBPYGXGULr5H7Z9zIIUyNWlAKBBgRVZKOqbMYV5?=
 =?us-ascii?Q?rVbitJOB8kALErecoF7DplwGxxnLj99NqkgUN+OVOc9I4U/jPpmpvN7PJtNi?=
 =?us-ascii?Q?X0zQLl8W83LIKqNJiXM2kisuh1ljoGPgo8QV1t9GRBHuFzXg+jZSN3vkTNPf?=
 =?us-ascii?Q?8GDKICBXk+MQOnptXYd7a8o2RphHLMR86DfhIWIav2AsUgi/MLYcuyuGkF77?=
 =?us-ascii?Q?niI0O0rKtEb98Z4s8tPg4xfT1wDFBLXUGsv7zOtJdi9ouw4vv44bOk9wZBsa?=
 =?us-ascii?Q?7lmrU+y2jfJjcFRaOaO0itgMqE0qu8+25MHqFjXomwq+7lCj5rmuqA14kqkB?=
 =?us-ascii?Q?+aBoIl1OY3gIcOGD1Yj2DuajDo5LNL/XvYn6oKFj+KG+afA9/qbaDbcKcppo?=
 =?us-ascii?Q?l1Qn7geWf+yjJmazcclGMRoa9yDuQUDXtSpOHzn6z+kqDKa60LnC/hPuYzf+?=
 =?us-ascii?Q?256zGDgmfgnp123pyUhEcJAdwbQVC9WK1SSJGMhT6QpF7pxiDJAaoEXKF5FH?=
 =?us-ascii?Q?SGzO2wiPZ8YmGB2PCJadWZ9MF9Ee8EUIfWKeokV7Pt5u8vOFvuuoPAUYvyq2?=
 =?us-ascii?Q?Z7csJXH8s2Y6iirRaIbp0Ez80ftI2n69QZdcym1MoTwHUsqDYyxCRrqlBqyl?=
 =?us-ascii?Q?RjJN1d77/fLxDb3XjJMqMg0kwoeWM97dEkleN1fBnb5+mN9sQyhMmcf1DUx7?=
 =?us-ascii?Q?cArnfuvLjfaHLDEwEvwVywj1J/SFp3zsR5MQiw4z8ZqtE2A94UH2MuFaW9V3?=
 =?us-ascii?Q?0DP9w7dZKoCZ28KBDI0sC3ZAGfkgDxHmbyBw+TwkgNAVfQT80SwNTOiI7yyJ?=
 =?us-ascii?Q?ToJqIX8gUQSGq2aztKghV1O5B9lHhGp39fekmPp0VR49rs90+RwD2ynjSbCu?=
 =?us-ascii?Q?30FnfL5+p3FTbPmGpFFg4Df3lrpIBIRtrwgbvzD3xycY9v6utDaOmFtyrG8K?=
 =?us-ascii?Q?JQpAhotdZBXiIpWp8XK23u0RmJLMxOcDhI3KIS5LjoiRD+N2UdmxGyPWUxWP?=
 =?us-ascii?Q?PPXBe2L82od5cgRdEsvEViqI9iI5CaHT2ObpGTVrRx1QbbMQfokihNGu9sow?=
 =?us-ascii?Q?xmQjbOMx0XINaCcah2Z2kiyzSRuPxv+lTltpSYMij6B6AhxV0R/lMo1t7oJZ?=
 =?us-ascii?Q?FjkPZugr4bnhiAoBTBPdSdS8s+X8s99BZeK/T+uVPsGDHZAhM0n00PZpQ7P4?=
 =?us-ascii?Q?F8FLkCKm/WSBLylqlDH4OByjLQawTSPj/d3QBbTSG/pLwL9rFH/A0h4tcwwY?=
 =?us-ascii?Q?P5Ft7JRDVfoPJ/C5PybmIwhMKR/N3y9m0fpdqDvLYcK4qtoCKjikq/vcYqqj?=
 =?us-ascii?Q?xPWHGDvBmX3L5gQbEMHeojxSMh7cb1oNDBCHK6+Mq6umAraCeaiwHLAwZWhU?=
 =?us-ascii?Q?cuCN2VtFp0/QzlrA48SFePEv0nGdALqhoqzl2119WNbiSz2Fi8Kwiicq01PS?=
 =?us-ascii?Q?jCRO9QX238blb5ejfA8p3kCdjL5CV0ukF5CeMWMcR22hA8R15x/XkTyd/3WN?=
 =?us-ascii?Q?IIZ4Aty/gDfD3Rknr/1ZYdJZOVrnoOjb/7NmUrt/B00aPzssOUMoANS4rLW/?=
 =?us-ascii?Q?el5KIKFza/57034rzT36xXTBskhlGpucullMB/UW?=
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-Network-Message-Id: c7cc4da8-5645-4882-45be-08db0dd0f969
X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2023 14:45:39.3560
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: 1Q6xdr5cJ5y+KWAWhh3X/7E1Ew5HwJ2ZIyC/JvqrtC1GPUSHkJDggR0T8H8ZcRsO
X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6028
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Mon, Feb 13, 2023 at 02:24:40AM +0000, Tian, Kevin wrote:

> > This is because the cache tag and the io page table top are in
> > different 64 bit words so atomic writes don't cover both, and thus the
> > IOMMU HW could tear the two stores and mismatch the cache tag to the
> > table top. This would corrupt the cache.
> 
> VT-d spec recommends using 128bit cmpxchg instruction to update
> page table pointer and DID together.

Oh really? Such a thing exists? That neat!

Jason