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Add usb3 node at common connect subsystem. Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8-ss-conn.dtsi | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 4852760adeee..94692cee25a0 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -138,6 +138,56 @@ fec2: ethernet@5b050000 { status = "disabled"; }; + usbotg3: usb@5b110000 { + compatible = "fsl,imx8qm-usb3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x5b110000 0x10000>; + clocks = <&usb3_lpcg IMX_LPCG_CLK_1>, + <&usb3_lpcg IMX_LPCG_CLK_0>, + <&usb3_lpcg IMX_LPCG_CLK_7>, + <&usb3_lpcg IMX_LPCG_CLK_4>, + <&usb3_lpcg IMX_LPCG_CLK_5>; + clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", + "usb3_ipg_clk", "usb3_core_pclk"; + assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <125000000>, <12000000>, <250000000>; + power-domains = <&pd IMX_SC_R_USB_2>; + status = "disabled"; + + usbotg3_cdns3: usb@5b120000 { + compatible = "cdns,usb3"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + interrupt-names = "host", "peripheral", "otg", "wakeup"; + reg = <0x5b130000 0x10000>, /* memory area for HOST registers */ + <0x5b140000 0x10000>, /* memory area for DEVICE registers */ + <0x5b120000 0x10000>; /* memory area for OTG/DRD registers */ + reg-names = "xhci", "dev", "otg"; + phys = <&usb3_phy>; + phy-names = "cdns3,usb3-phy"; + status = "disabled"; + }; + }; + + usb3_phy: usb-phy@5b160000 { + compatible = "nxp,salvo-phy"; + reg = <0x5b160000 0x40000>; + clocks = <&usb3_lpcg IMX_LPCG_CLK_6>; + clock-names = "salvo_phy_clk"; + power-domains = <&pd IMX_SC_R_USB_2_PHY>; + #phy-cells = <0>; + status = "disabled"; + }; + /* LPCG clocks */ sdhc0_lpcg: clock-controller@5b200000 { compatible = "fsl,imx8qxp-lpcg"; @@ -234,4 +284,26 @@ usb2_lpcg: clock-controller@5b270000 { clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk"; power-domains = <&pd IMX_SC_R_USB_0_PHY>; }; + + usb3_lpcg: clock-controller@5b280000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b280000 0x10000>; + #clock-cells = <1>; + clock-indices = , , + , , + , ; + clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>, + <&conn_ipg_clk>, + <&conn_ipg_clk>, + <&conn_ipg_clk>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; + clock-output-names = "usb3_app_clk", + "usb3_lpm_clk", + "usb3_ipg_clk", + "usb3_core_pclk", + "usb3_phy_clk", + "usb3_aclk"; + power-domains = <&pd IMX_SC_R_USB_2_PHY>; + }; }; -- 2.34.1