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charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20230214121440epcas5p46db82a141c3e2664cff4b290b49c3938 References: <20230214121333.1837-1-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Common application logic register read and write functions used for better readability. Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-samsung.c | 54 ++++++++++++------------ 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-samsung.c b/drivers/pci/controller/dwc/pci-samsung.c index be0177fcd763..e6e2a8ab4403 100644 --- a/drivers/pci/controller/dwc/pci-samsung.c +++ b/drivers/pci/controller/dwc/pci-samsung.c @@ -79,63 +79,63 @@ static void exynos_pcie_deinit_clk_resources(struct samsung_pcie *sp) clk_bulk_disable_unprepare(sp->clk_cnt, sp->clks); } -static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) +static void samsung_pcie_appl_writel(struct samsung_pcie *sp, u32 val, u32 reg) { - writel(val, base + reg); + writel(val, sp->appl_base + reg); } -static u32 exynos_pcie_readl(void __iomem *base, u32 reg) +static unsigned int samsung_pcie_appl_readl(struct samsung_pcie *sp, u32 reg) { - return readl(base + reg); + return readl(sp->appl_base + reg); } static void exynos_pcie_sideband_dbi_w_mode(struct samsung_pcie *sp, bool on) { u32 val; - val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_APPL_SLV_AWMISC); + val = samsung_pcie_appl_readl(sp, EXYNOS_PCIE_APPL_SLV_AWMISC); if (on) val |= EXYNOS_PCIE_APPL_SLV_DBI_ENABLE; else val &= ~EXYNOS_PCIE_APPL_SLV_DBI_ENABLE; - exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_APPL_SLV_AWMISC); + samsung_pcie_appl_writel(sp, val, EXYNOS_PCIE_APPL_SLV_AWMISC); } static void exynos_pcie_sideband_dbi_r_mode(struct samsung_pcie *sp, bool on) { u32 val; - val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_APPL_SLV_ARMISC); + val = samsung_pcie_appl_readl(sp, EXYNOS_PCIE_APPL_SLV_ARMISC); if (on) val |= EXYNOS_PCIE_APPL_SLV_DBI_ENABLE; else val &= ~EXYNOS_PCIE_APPL_SLV_DBI_ENABLE; - exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_APPL_SLV_ARMISC); + samsung_pcie_appl_writel(sp, val, EXYNOS_PCIE_APPL_SLV_ARMISC); } static void exynos_pcie_assert_core_reset(struct samsung_pcie *sp) { u32 val; - val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_CORE_RESET); + val = samsung_pcie_appl_readl(sp, EXYNOS_PCIE_CORE_RESET); val &= ~EXYNOS_PCIE_CORE_RESET_ENABLE; - exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_CORE_RESET); - exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_STICKY_RESET); - exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_NONSTICKY_RESET); + samsung_pcie_appl_writel(sp, val, EXYNOS_PCIE_CORE_RESET); + samsung_pcie_appl_writel(sp, 0, EXYNOS_PCIE_STICKY_RESET); + samsung_pcie_appl_writel(sp, 0, EXYNOS_PCIE_NONSTICKY_RESET); } static void exynos_pcie_deassert_core_reset(struct samsung_pcie *sp) { u32 val; - val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_CORE_RESET); + val = samsung_pcie_appl_readl(sp, EXYNOS_PCIE_CORE_RESET); val |= EXYNOS_PCIE_CORE_RESET_ENABLE; - exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_CORE_RESET); - exynos_pcie_writel(sp->appl_base, 1, EXYNOS_PCIE_STICKY_RESET); - exynos_pcie_writel(sp->appl_base, 1, EXYNOS_PCIE_NONSTICKY_RESET); - exynos_pcie_writel(sp->appl_base, 1, EXYNOS_PCIE_APP_INIT_RESET); - exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_APP_INIT_RESET); + samsung_pcie_appl_writel(sp, val, EXYNOS_PCIE_CORE_RESET); + samsung_pcie_appl_writel(sp, 1, EXYNOS_PCIE_STICKY_RESET); + samsung_pcie_appl_writel(sp, 1, EXYNOS_PCIE_NONSTICKY_RESET); + samsung_pcie_appl_writel(sp, 1, EXYNOS_PCIE_APP_INIT_RESET); + samsung_pcie_appl_writel(sp, 0, EXYNOS_PCIE_APP_INIT_RESET); } static int exynos_pcie_start_link(struct dw_pcie *pci) @@ -143,21 +143,21 @@ static int exynos_pcie_start_link(struct dw_pcie *pci) struct samsung_pcie *sp = to_samsung_pcie(pci); u32 val; - val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_SW_WAKE); + val = samsung_pcie_appl_readl(sp, EXYNOS_PCIE_SW_WAKE); val &= ~EXYNOS_PCIE_BUS_EN; - exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_SW_WAKE); + samsung_pcie_appl_writel(sp, val, EXYNOS_PCIE_SW_WAKE); /* assert LTSSM enable */ - exynos_pcie_writel(sp->appl_base, EXYNOS_PCIE_APPL_LTSSM_ENABLE, + samsung_pcie_appl_writel(sp, EXYNOS_PCIE_APPL_LTSSM_ENABLE, EXYNOS_PCIE_APP_LTSSM_ENABLE); return 0; } static void exynos_pcie_clear_irq_pulse(struct samsung_pcie *sp) { - u32 val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_IRQ_PULSE); + u32 val = samsung_pcie_appl_readl(sp, EXYNOS_PCIE_IRQ_PULSE); - exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_IRQ_PULSE); + samsung_pcie_appl_writel(sp, val, EXYNOS_PCIE_IRQ_PULSE); } static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) @@ -173,9 +173,9 @@ static void exynos_pcie_enable_irq_pulse(struct samsung_pcie *sp) u32 val = EXYNOS_IRQ_INTA_ASSERT | EXYNOS_IRQ_INTB_ASSERT | EXYNOS_IRQ_INTC_ASSERT | EXYNOS_IRQ_INTD_ASSERT; - exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_IRQ_EN_PULSE); - exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_IRQ_EN_LEVEL); - exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_IRQ_EN_SPECIAL); + samsung_pcie_appl_writel(sp, val, EXYNOS_PCIE_IRQ_EN_PULSE); + samsung_pcie_appl_writel(sp, 0, EXYNOS_PCIE_IRQ_EN_LEVEL); + samsung_pcie_appl_writel(sp, 0, EXYNOS_PCIE_IRQ_EN_SPECIAL); } static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, @@ -232,7 +232,7 @@ static struct pci_ops exynos_pci_ops = { static int exynos_pcie_link_up(struct dw_pcie *pci) { struct samsung_pcie *sp = to_samsung_pcie(pci); - u32 val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_APPL_RDLH_LINKUP); + u32 val = samsung_pcie_appl_readl(sp, EXYNOS_PCIE_APPL_RDLH_LINKUP); return (val & EXYNOS_PCIE_APPL_XMLH_LINKUP); } -- 2.17.1