Date:   Tue, 14 Feb 2023 18:17:45 +0000
From:   Conor Dooley <conor@kernel.org>
To:     Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Cc:     Ben Dooks <ben.dooks@codethink.co.uk>, Lee Jones <lee@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>,
        Emil Renner Berthing <kernel@esmil.dk>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Giuseppe Cavallaro <peppe.cavallaro@st.com>,
        Alexandre Torgue <alexandre.torgue@foss.st.com>,
        Jose Abreu <joabreu@synopsys.com>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>,
        Richard Cochran <richardcochran@gmail.com>,
        Sagar Kadam <sagar.kadam@sifive.com>,
        Yanhong Wang <yanhong.wang@starfivetech.com>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        netdev@vger.kernel.org, linux-riscv@lists.infradead.org,
        linux-stm32@st-md-mailman.stormreply.com,
        linux-arm-kernel@lists.infradead.org, kernel@collabora.com
Subject: Re: [PATCH 05/12] riscv: Implement non-coherent DMA support via
 SiFive cache flushing
Message-ID: <Y+vQScKTumiXe8n3@spud>
References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com>
 <20230211031821.976408-6-cristian.ciocaltea@collabora.com>
 <f1a6c357-b7e0-2869-72e0-e850b63e6ca9@codethink.co.uk>
 <3256853a-d744-4a41-41b6-752b5c95eedc@collabora.com>
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On Tue, Feb 14, 2023 at 08:06:49PM +0200, Cristian Ciocaltea wrote:
> On 2/13/23 10:30, Ben Dooks wrote:
> > On 11/02/2023 03:18, Cristian Ciocaltea wrote:
> > > From: Emil Renner Berthing <kernel@esmil.dk>

> > > diff --git a/arch/riscv/mm/dma-noncoherent.c
> > > b/arch/riscv/mm/dma-noncoherent.c
> > > index d919efab6eba..e07e53aea537 100644
> > > --- a/arch/riscv/mm/dma-noncoherent.c
> > > +++ b/arch/riscv/mm/dma-noncoherent.c
> > > @@ -9,14 +9,21 @@
> > > =A0 #include <linux/dma-map-ops.h>
> > > =A0 #include <linux/mm.h>
> > > =A0 #include <asm/cacheflush.h>
> > > +#include <soc/sifive/sifive_ccache.h>
> > > =A0 static bool noncoherent_supported;
> > > =A0 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
> > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 enum dma_da=
ta_direction dir)
> > > =A0 {
> > > -=A0=A0=A0 void *vaddr =3D phys_to_virt(paddr);
> > > +=A0=A0=A0 void *vaddr;
> > > +=A0=A0=A0 if (sifive_ccache_handle_noncoherent()) {
> > > +=A0=A0=A0=A0=A0=A0=A0 sifive_ccache_flush_range(paddr, size);
> > > +=A0=A0=A0=A0=A0=A0=A0 return;
> > > +=A0=A0=A0 }
> > > +
> > > +=A0=A0=A0 vaddr =3D phys_to_virt(paddr);
> > > =A0=A0=A0=A0=A0 switch (dir) {
> > > =A0=A0=A0=A0=A0 case DMA_TO_DEVICE:
> > > =A0=A0=A0=A0=A0=A0=A0=A0=A0 ALT_CMO_OP(clean, vaddr, size, riscv_cbom=
_block_size);
> > > @@ -35,8 +42,14 @@ void arch_sync_dma_for_device(phys_addr_t paddr,
> > > size_t size,
> > > =A0 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
> > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 enum dma_data_direct=
ion dir)
> > > =A0 {
> > > -=A0=A0=A0 void *vaddr =3D phys_to_virt(paddr);
> > > +=A0=A0=A0 void *vaddr;
> > > +
> > > +=A0=A0=A0 if (sifive_ccache_handle_noncoherent()) {
> > > +=A0=A0=A0=A0=A0=A0=A0 sifive_ccache_flush_range(paddr, size);
> > > +=A0=A0=A0=A0=A0=A0=A0 return;
> > > +=A0=A0=A0 }
> >=20
> > ok, what happens if we have an system where the ccache and another level
> > of cache also requires maintenance operations?

TBH, I'd hope that a system with that complexity is also not trying to
manage the cache in this manner!

> According to [1], the handling of non-coherent DMA on RISC-V is currently
> being worked on, so I will respin the series as soon as the proper support
> arrives.

But yeah, once that stuff lands we can carry out these operations only
for the platforms that need/"need" it.

Cheers,
Conor.


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