Date:   Tue, 14 Feb 2023 21:38:42 +0000
From:   Conor Dooley <conor@kernel.org>
To:     Evan Green <evan@rivosinc.com>
Cc:     Palmer Dabbelt <palmer@rivosinc.com>, vineetg@rivosinc.com,
        heiko@sntech.de, slewis@rivosinc.com,
        Albert Ou <aou@eecs.berkeley.edu>,
        Anup Patel <apatel@ventanamicro.com>,
        Atish Patra <atishp@rivosinc.com>,
        Conor Dooley <conor.dooley@microchip.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Qinglin Pan <panqinglin2020@iscas.ac.cn>,
        Randy Dunlap <rdunlap@infradead.org>,
        Sunil V L <sunilvl@ventanamicro.com>,
        linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 1/6] RISC-V: Move struct riscv_cpuinfo to new header
Message-ID: <Y+v/Yu/ELfzx954s@spud>
References: <20230206201455.1790329-1-evan@rivosinc.com>
 <20230206201455.1790329-2-evan@rivosinc.com>
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        protocol="application/pgp-signature"; boundary="f5tYJzmdjbJLMszm"
Content-Disposition: inline
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--f5tYJzmdjbJLMszm
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
Content-Transfer-Encoding: quoted-printable

On Mon, Feb 06, 2023 at 12:14:50PM -0800, Evan Green wrote:
> In preparation for tracking and exposing microarchitectural details to
> userspace (like whether or not unaligned accesses are fast), move the
> riscv_cpuinfo struct out to its own new cpufeatures.h header. It will
> need to be used by more than just cpu.c.
>=20
> Signed-off-by: Evan Green <evan@rivosinc.com>
> ---
>=20
> (no changes since v1)

Really? I don't recall seeing this patch in v1? ;)

>=20
>  arch/riscv/include/asm/cpufeature.h | 21 +++++++++++++++++++++
>  arch/riscv/kernel/cpu.c             |  8 ++------
>  2 files changed, 23 insertions(+), 6 deletions(-)
>  create mode 100644 arch/riscv/include/asm/cpufeature.h
>=20
> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm=
/cpufeature.h
> new file mode 100644
> index 000000000000..66c251d98290
> --- /dev/null
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright 2022 Rivos, Inc
> + */
> +
> +#ifndef _ASM_CPUFEATURE_H
> +#define _ASM_CPUFEATURE_H
> +
> +/*
> + * These are probed via a device_initcall(), via either the SBI or direc=
tly
> + * from the cooresponding CSRs.

May as well fix the typo here while we are moving the code & a respin is
required anyway.

I'm sure we'll need this patch regardless of approach, so:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

--f5tYJzmdjbJLMszm
Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY+v/YgAKCRB4tDGHoIJi
0tZUAP9alaj90UKMameldRPMqw+IPDy0llCUwKgwfXm1M4dLnwD9Fs25ZbsYQRWN
myGAiC3u18dRkuCDk/kRsy20aoskSQU=
=mKq5
-----END PGP SIGNATURE-----

--f5tYJzmdjbJLMszm--