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Subject: RE: [PATCH 3/6] clk: samsung: clk-pll: Implement pll0818x PLL type
Reply-To: chanho61.park@samsung.com
Sender: CHANHO PARK <chanho61.park@samsung.com>
From:   CHANHO PARK <chanho61.park@samsung.com>
To:     Sam Protsenko <semen.protsenko@linaro.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Chanwoo Choi <cw00.choi@samsung.com>,
        Sylwester Nawrocki <s.nawrocki@samsung.com>,
        Rob Herring <robh+dt@kernel.org>
CC:     David Virag <virag.david003@gmail.com>,
        ALIM AKHTAR <alim.akhtar@samsung.com>,
        Sumit Semwal <sumit.semwal@linaro.org>,
        Tomasz Figa <tomasz.figa@gmail.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        "linux-samsung-soc@vger.kernel.org" 
        <linux-samsung-soc@vger.kernel.org>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
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Date:   Wed, 15 Feb 2023 11:38:09 +0900
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Precedence: bulk

> Subject: [PATCH 3/6] clk: samsung: clk-pll: Implement pll0818x PLL type
> 
> pll0818x PLL is used in Exynos850 SoC for CMU_G3D PLL. Operation-wise,
> pll0818x is the same as pll0822x. The only difference is:
>   - pl0822x is integer PLL with Middle FVCO (950 to 2400 MHz)
>   - pl0818x is integer PLL with Low FVCO (600 to 1200 MHz)
> 
> Add pll0818x type as an alias to pll0822x.
> 
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>

Reviewed-by: Chanho Park <chanho61.park@samsung.com>

> ---
>  drivers/clk/samsung/clk-pll.c | 1 +
>  drivers/clk/samsung/clk-pll.h | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 5ceac4c25c1c..74934c6182ce 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -1314,6 +1314,7 @@ static void __init _samsung_clk_register_pll(struct
> samsung_clk_provider *ctx,
>  			init.ops = &samsung_pll35xx_clk_ops;
>  		break;
>  	case pll_1417x:
> +	case pll_0818x:
>  	case pll_0822x:
>  		pll->enable_offs = PLL0822X_ENABLE_SHIFT;
>  		pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; diff --git
> a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index
> 5d5a58d40e7e..0725d485c6ee 100644
> --- a/drivers/clk/samsung/clk-pll.h
> +++ b/drivers/clk/samsung/clk-pll.h
> @@ -34,6 +34,7 @@ enum samsung_pll_type {
>  	pll_1451x,
>  	pll_1452x,
>  	pll_1460x,
> +	pll_0818x,
>  	pll_0822x,
>  	pll_0831x,
>  	pll_142xx,
> --
> 2.39.1