Date:   Tue, 14 Feb 2023 19:17:11 -0800 (PST)
Subject:     Re: [PATCH v16 0/9] RISC-V IPI Improvements
In-Reply-To: <86357k1ihd.wl-maz@kernel.org>
CC:     apatel@ventanamicro.com, Paul Walmsley <paul.walmsley@sifive.com>,
        tglx@linutronix.de, daniel.lezcano@linaro.org, marcan@marcan.st,
        sven@svenpeter.dev, alyssa@rosenzweig.io, atishp@atishpatra.org,
        Alistair Francis <Alistair.Francis@wdc.com>,
        anup@brainfault.org, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org, asahi@lists.linux.dev
From:   Palmer Dabbelt <palmer@dabbelt.com>
To:     Marc Zyngier <maz@kernel.org>
Message-ID: <mhng-a886c4b4-d748-420f-889b-76ada4f9a432@palmer-ri-x1c9>
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On Sun, 05 Feb 2023 03:04:14 PST (-0800), Marc Zyngier wrote:
> On Tue, 03 Jan 2023 14:12:12 +0000,
> Anup Patel <apatel@ventanamicro.com> wrote:
>>
>> This series aims to improve IPI support in Linux RISC-V in following ways:
>>  1) Treat IPIs as normal per-CPU interrupts instead of having custom RISC-V
>>     specific hooks. This also makes Linux RISC-V IPI support aligned with
>>     other architectures.
>>  2) Remote TLB flushes and icache flushes should prefer local IPIs instead
>>     of SBI calls whenever we have specialized hardware (such as RISC-V AIA
>>     IMSIC and RISC-V SWI) which allows S-mode software to directly inject
>>     IPIs without any assistance from M-mode runtime firmware.
>
> [...]
>
> I'm queuing patches 3 and 9 via the irqchip tree as they are
> standalone.
>
> For the rest, I need an Ack from the riscv maintainers as they change
> a large amount of arch-specific code, and the couple of irqchip
> patches depend on these changes.
>
> Palmer, Paul?

I haven't gotten time to give this a proper review, but I think we've 
got enough of a mess with our interrupt handling that it doesn't really 
matter so

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

if you want to take it for this cycle that's fine with me, but I'm also 
fine holding off so it can have a while to bake in linux-next -- there's 
no real rush for any of this, as there's no hardware yet.

>
> Thanks,
>
> 	M.