Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F37DC6379F for ; Wed, 15 Feb 2023 08:27:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233921AbjBOI10 (ORCPT ); Wed, 15 Feb 2023 03:27:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233909AbjBOI1Y (ORCPT ); Wed, 15 Feb 2023 03:27:24 -0500 Received: from relay10.mail.gandi.net (relay10.mail.gandi.net [IPv6:2001:4b98:dc4:8::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 432A2367E8; Wed, 15 Feb 2023 00:27:11 -0800 (PST) Received: (Authenticated sender: clement.leger@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id E1034240007; Wed, 15 Feb 2023 08:27:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1676449629; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2TjOYJpQY/rMAj42OkOWvcZQditWdAM0UKPzvzdp8/g=; b=Y01a+/BUoIPDLZROoJ7+KPPD6XkOyDZLGDR3flpg+BpXQWygnkZpyTdT1BH4hh8AanUnlq ymmVw+hv4tKpdXzZEw7WmFndG217Y6ErYdyoteAN6gFucuRv6mN60PrYYUogBrSc1++hqa WhtELk56Y6eLjuiuZOkjZq9N2L6mjLSqOJonvXr4s9DAS9i+EDK29Eq1jTsFEhH7wKmEOt b62akRnwg3VyAz7LOlr3+m+xhmJwFJlp8F89IlhUn4NnTExHi2TC5PtVq++fWeFBMI2ykE qCumpnzlF0lJ39hEoAvt9zbqiiIzD0b/OI0UYXdgvK20fsnZAFTN0clnpu2YXg== Date: Wed, 15 Feb 2023 09:29:33 +0100 From: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= To: Geert Uytterhoeven Cc: Magnus Damm , Rob Herring , Krzysztof Kozlowski , Thomas Petazzoni , Herve Codina , =?UTF-8?B?TWlxdcOobA==?= Raynal , Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gareth Williams Subject: Re: [PATCH v2 2/2] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree Message-ID: <20230215092933.2f71ece0@fixe.home> In-Reply-To: References: <20230209133507.150571-1-clement.leger@bootlin.com> <20230209133507.150571-3-clement.leger@bootlin.com> Organization: Bootlin X-Mailer: Claws Mail 4.1.1 (GTK 3.24.36; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Le Tue, 14 Feb 2023 17:25:14 +0100, Geert Uytterhoeven a =C3=A9crit : > Hi Cl=C3=A9ment, >=20 > CC Gareth >=20 > On Thu, Feb 9, 2023 at 2:32 PM Cl=C3=A9ment L=C3=A9ger wrote: > > The EB board (Expansion board) supports both RZ/N1D and RZ-N1S. Since t= his > > configuration targets only the RZ/N1D, it is named r9a06g032-rzn1d400-e= b. > > It adds support for the 2 additional switch ports (port C and D) that a= re > > available on that board. > > > > Signed-off-by: Cl=C3=A9ment L=C3=A9ger =20 >=20 > Thanks for your patch! >=20 > > --- /dev/null > > +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-eb.dts > > @@ -0,0 +1,94 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Device Tree Source for the RZN1D-EB Board > > + * > > + * Copyright (C) 2023 Schneider-Electric > > + * > > + */ > > + > > +#include "r9a06g032-rzn1d400-db.dts" > > + > > +/ { > > + model =3D "RZN1D-EB Board"; > > + compatible =3D "renesas,rzn1d400-eb", "renesas,rzn1d400-db", > > + "renesas,r9a06g032"; > > +}; > > + > > +&mii_conv2 { > > + renesas,miic-input =3D ; > > + status =3D "okay"; > > +}; > > + > > +&mii_conv3 { > > + renesas,miic-input =3D ; > > + status =3D "okay"; > > +}; > > + > > +&pinctrl{ > > + pins_eth1: pins-eth1 { > > + pinmux =3D , > > + , > > + , > > + , > > + , > > + , > > + , > > + , > > + , > > + , > > + , > > + ; > > + drive-strength =3D <6>; > > + bias-disable; > > + }; > > + > > + pins_eth2: pins-eth2 { > > + pinmux =3D , > > + , > > + , > > + , > > + , > > + , > > + , > > + , > > + , > > + , > > + , > > + ; > > + drive-strength =3D <6>; > > + bias-disable; > > + }; > > +}; > > + > > +&switch { > > + pinctrl-names =3D "default"; =20 >=20 > No need to specify pinctrl-names, as it is inherited from > r9a06g032-rzn1d400-db.dts. Acked. >=20 > > + pinctrl-0 =3D <&pins_eth1>, <&pins_eth2>, <&pins_eth3>, <&pins_= eth4>, > > + <&pins_mdio1>; > > + > > + mdio { > > + /* CN15 and CN16 switches must be configured in MDIO2 m= ode */ > > + switch0phy1: ethernet-phy@1 { > > + reg =3D <1>; > > + marvell,reg-init =3D <3 16 0 0x1010>; =20 >=20 > marvell,reg-init is not documented in any DT bindings document? Indeed, this is not somethiong that should be made available here. It's only inverting the LED polarity but supported by some internal patch. I'll remove that. --=20 Cl=C3=A9ment L=C3=A9ger, Embedded Linux and Kernel engineer at Bootlin https://bootlin.com