Date:   Wed, 15 Feb 2023 09:58:48 +0100
From:   Greg KH <gregkh@linuxfoundation.org>
To:     Michael Walle <michael@walle.cc>
Cc:     Kumaravel.Thiagarajan@microchip.com,
        Tharunkumar.Pasumarthi@microchip.com, UNGLinuxDriver@microchip.com,
        arnd@arndb.de, linux-gpio@vger.kernel.org,
        linux-kernel@vger.kernel.org, srinivas.kandagatla@linaro.org
Subject: Re: [PATCH v5 char-misc-next] misc: microchip: pci1xxxx: Add
 OTP/EEPROM driver for the pci1xxxx switch
Message-ID: <Y+yeyNCA48IbKOKC@kroah.com>
References: <20230212035743.231353-1-tharunkumar.pasumarthi@microchip.com>
 <20230214082804.2761756-1-michael@walle.cc>
 <BN8PR11MB36680842890C294566A156C3E9A39@BN8PR11MB3668.namprd11.prod.outlook.com>
 <7276bef47792e489abd093e4bd0044de@walle.cc>
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On Wed, Feb 15, 2023 at 09:20:10AM +0100, Michael Walle wrote:
> Hi,
> 
> > > > Microchip's pci1xxxx is an unmanaged PCIe3.1a switch for consumer,
> > > > industrial, and automotive applications. This switch integrates OTP
> > > > and EEPROM to enable customization of the part in the field. This
> > > > patch provides the OTP/EEPROM driver to support the same.
> > > 
> > > Why isn't this driver using the nvmem subsystem which is usually
> > > used for
> > > OTP and EEPROM?
> > Michael, these OTP and EEPROM memories do not have any fixed location
> > registers which
> > store values (Eg. mac address, config parameters, etc) at fixed offsets.
> > It stores a bunch of records, each of which has some data to be
> > written into the device's
> > hardware registers at different locations. These records are directly
> > consumed by the hardware
> > and interpreted without the involvement of the software.
> > Therefore, we don't require any OTP / EEPROM register map to be input
> > to the OS / driver through
> > device tree or board files.
> > I only had to enumerate two separate block devices using the driver so
> > that the config binary files can be
> > overlayed using the dd command.
> > Since this is not fitting like a conventional nvme device, I didn't
> > choose the nvme subsystem.
> > Please let me know your thoughts / comments if any.
> 
> So this is only for provisioning. i.e. during manufacturing a board
> which uses this PCI bridge? There are no kernel users, nor is
> there a common interface towards user-space. But just some block
> device (why not a char device?) exposed to userspace. I presume
> there is a companion userspace application for it? Why do you take
> the extra step and have a (random) kernel interface, you could
> also just access the PCI device directly from userspace within your
> companion application, e.g. through libpci.

Yeah, why not just use userspace, I missed that, thanks!

greg k-h