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[209.85.128.170]) by smtp.gmail.com with ESMTPSA id b1-20020a378001000000b0073b597ce5f8sm3286338qkd.120.2023.02.15.03.32.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 15 Feb 2023 03:32:05 -0800 (PST) Received: by mail-yw1-f170.google.com with SMTP id 00721157ae682-530b9a0a789so33265147b3.13; Wed, 15 Feb 2023 03:32:04 -0800 (PST) X-Received: by 2002:a0d:f347:0:b0:4fc:962d:7dc1 with SMTP id c68-20020a0df347000000b004fc962d7dc1mr220614ywf.301.1676460724637; Wed, 15 Feb 2023 03:32:04 -0800 (PST) MIME-Version: 1.0 References: <20230209133507.150571-1-clement.leger@bootlin.com> <20230209133507.150571-3-clement.leger@bootlin.com> <20230215092933.2f71ece0@fixe.home> <20230215115441.361aed53@fixe.home> In-Reply-To: <20230215115441.361aed53@fixe.home> From: Geert Uytterhoeven Date: Wed, 15 Feb 2023 12:31:52 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 2/2] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree To: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= Cc: Magnus Damm , Rob Herring , Krzysztof Kozlowski , Thomas Petazzoni , Herve Codina , =?UTF-8?Q?Miqu=C3=A8l_Raynal?= , Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gareth Williams Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Clément, On Wed, Feb 15, 2023 at 11:52 AM Clément Léger wrote: > Le Wed, 15 Feb 2023 09:29:33 +0100, > Clément Léger a écrit : > > Le Tue, 14 Feb 2023 17:25:14 +0100, > > Geert Uytterhoeven a écrit : > > > On Thu, Feb 9, 2023 at 2:32 PM Clément Léger wrote: > > > > The EB board (Expansion board) supports both RZ/N1D and RZ-N1S. Since this > > > > configuration targets only the RZ/N1D, it is named r9a06g032-rzn1d400-eb. > > > > It adds support for the 2 additional switch ports (port C and D) that are > > > > available on that board. > > > > > > > > Signed-off-by: Clément Léger > > > > > > Thanks for your patch! > > > > > > > --- /dev/null > > > > +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-eb.dts > > > > + pinctrl-0 = <&pins_eth1>, <&pins_eth2>, <&pins_eth3>, <&pins_eth4>, > > > > + <&pins_mdio1>; > > > > + > > > > + mdio { > > > > + /* CN15 and CN16 switches must be configured in MDIO2 mode */ > > > > + switch0phy1: ethernet-phy@1 { > > > > + reg = <1>; > > > > + marvell,reg-init = <3 16 0 0x1010>; > > > > > > marvell,reg-init is not documented in any DT bindings document? > > > > Indeed, this is not somethiong that should be made available here. It's > > only inverting the LED polarity but supported by some internal patch. > > I'll remove that. > I actually was confused by a property I added in another device-tree but > marvell,reg-init exists, is handled by the marvell phy driver and used > in a few device-trees. Strangely, it is not documented anywhere. So I > can either remove that (and the LED won't work properly) or let it live > depending on what you prefer. In that case, please keep it. But the property really should be documented, one day... Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds