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References: <1676426457-1389-1-git-send-email-cy_huang@richtek.com>
 <1676426457-1389-2-git-send-email-cy_huang@richtek.com> <Y+zYIyaWt1tQcUt7@sirena.org.uk>
In-Reply-To: <Y+zYIyaWt1tQcUt7@sirena.org.uk>
From:   ChiYuan Huang <u0084500@gmail.com>
Date:   Wed, 15 Feb 2023 21:30:21 +0800
Message-ID: <CADiBU38MztMgusoCCGfEt2fdNhB7hC=4t3h_UN6-3s3FEvpXgQ@mail.gmail.com>
Subject: Re: [PATCH 1/2] dt-bindings: regulator: Add bindings for Richtek RT5739
To:     Mark Brown <broonie@kernel.org>
Cc:     cy_huang@richtek.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, lgirdwood@gmail.com,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
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Hi,

Mark Brown <broonie@kernel.org> =E6=96=BC 2023=E5=B9=B42=E6=9C=8815=E6=97=
=A5 =E9=80=B1=E4=B8=89 =E4=B8=8B=E5=8D=889:03=E5=AF=AB=E9=81=93=EF=BC=9A
>
> On Wed, Feb 15, 2023 at 10:00:56AM +0800, cy_huang@richtek.com wrote:
>
> > +  richtek,vsel-active-high:
> > +    description: |
> > +      If property is present, use the 'VSEL1' register group for buck =
control.
> > +      Else, use the 'VSEL0' register group. This depends on external h=
ardware
> > +      'VSEL' pin connecton.
> > +    type: boolean
>
> I would expect this to be GPIO controlled rather than fixed in
> the design, at least for some systems?  The name suggests it's
> supposed to control the polarity of a GPIO too.  Sadly we don't
> really have good infrastructure for fixed GPIOs AFAIK...  ideally
> this would be a GPIO and then if we need to hold it high then
> there would be some binding we could connect to the GPIO that
> says that.  We don't have that though so for now a fixed property
> might be OK.

It's most like two phase buck controllers internally. 'Vsel' to
control which buck output.
Each phase has its registers (voltage/enable/mode).
The common usage of 'vsel' pin is to connect the pin by SoC suspend/resume =
pin.
This can be used to implement system low power design (like as system
awake 0.6V, sleep 0.3V or sleep buck off).
I haven't seen the usage to connect it directly by GPIO.