Message-ID: <80dc58d3-0ea2-652d-7881-32a4526b5c14@amd.com>
Date:   Wed, 15 Feb 2023 22:38:57 +0700
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Subject: Re: [PATCH v2 1/3] KVM: SVM: Fix a benign off-by-one bug in AVIC
 physical table mask
Content-Language: en-US
To:     Sean Christopherson <seanjc@google.com>,
        Paolo Bonzini <pbonzini@redhat.com>
Cc:     kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
        Alejandro Jimenez <alejandro.j.jimenez@oracle.com>
References: <20230207002156.521736-1-seanjc@google.com>
 <20230207002156.521736-2-seanjc@google.com>
From:   "Suthikulpanit, Suravee" <suravee.suthikulpanit@amd.com>
In-Reply-To: <20230207002156.521736-2-seanjc@google.com>
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 =?utf-8?B?Vzk3Sy94QnEyeHRkOFRYa2F1WkdvKzFreVJ2OVprN0ZsMlFPem1kNkpHVTJB?=
 =?utf-8?B?eFlPak5zeU9vRmxUbkkvNkFEemx4cUdlaUw3Mk9iUTZUMlVhR0xtM2V5SnBS?=
 =?utf-8?B?ZHVDT1hNREZoNmF1Q0hYS2lSVGM2RXp1bVdRUEdjZzUxblBwVXVJU0c2aGNS?=
 =?utf-8?B?cTlsNHRrdGNQRVRkNCtLSFBQdHQwZFVRSXNnMHhwZmJJTWV4VlZlWDdjNXpx?=
 =?utf-8?B?eWlhUzIrUEx5Vk5LN0dZaURtdFF1Qnphc3JTNHJFM1l4Zzh4eDhaNFhldHgy?=
 =?utf-8?B?VVRUd0hHWHdEVEp0T3ZUOVJpMkRUdTJBWlNzZ2lZUVZ1VDBnbEtZTTJYdDJy?=
 =?utf-8?B?b1YxL1N2MHAyKzA0cWZadFZRNm00SXhOZVFyeUJlREZ6YW1OalpTa09ybHJq?=
 =?utf-8?B?bHFlelFZc3h4a3FJVHJuUlVmNCsybFdmUjZvUVV4SjdvVXJyZ0Q4TktSNUZM?=
 =?utf-8?B?b0h2TUJsdGtBUXlVZFoydDlBTzlQakg2MWtoZDFiQ1F6WDF3TzZtMDJCYlRu?=
 =?utf-8?B?M3YydUZDUGNqeE9mR0duakJMNUw5MWFtRmJHMFdFbVVPVy8vUzZ2dS9EN3lZ?=
 =?utf-8?B?c0JpUkIwZzl6eWNxRGJMQm9SY2Fza2xFUG90VmpuSzFabk5rYXh1OGpCZ1pH?=
 =?utf-8?B?TlREaDZHbEIzOFRsRVlCLy9WWDhucUNFSVErWWVBa04vVXpFYUp6dFdMa05U?=
 =?utf-8?B?K3FQSWlpYTBCOHFNSEppNWdnUWVQdEZHS3hzRnQ2WGdCcmgzeTFwdnNFVTZx?=
 =?utf-8?B?RkhZM1N2dk1TT0djRWFwOUo2cjFBNzBnaWhYOWdWUE5NYlV2MHEwSG56ZHl4?=
 =?utf-8?B?Sk5wTFBrSkgyeSs0Vys3WENXYU03cVpnbHUxZWJmdTBUK2FNYVhCeFZEM09K?=
 =?utf-8?B?c3lBWVhFQUNnS2htTlhkaVBNZUg5TWhaR1R2aTN0d2M5MnhZVm16aXFhU2pv?=
 =?utf-8?B?TjBpSEVqZVV6UW9qK3VnUU40SVpIVXF3Zk5HVGdvdC9XVGJHRmxFaHFZMncr?=
 =?utf-8?B?eGJVLzhzUHZ0NTI2MFkybHZweFBpSS9JT2JiVkFPZEl6VkFMU2czV1pGbXRR?=
 =?utf-8?B?SXZFRkc0WHNEQjRHSzc4MlNIZ1VMTWg0VmtOL3RlL3hQSDN3WFV1MG5BQ1Uz?=
 =?utf-8?B?WVNKeUtMeEtuUGc0MTJqLzdBSU1HT1R2djlTMVpqYzZhUk5HY05oSkl2elpJ?=
 =?utf-8?B?SzVFaE9zR1pxZEt5dEpZMWlWajV6WGw5OHp3OG9UTFM3RmZ4MllGUCtqaUJH?=
 =?utf-8?B?SUExZWJ6TE5LYWtHc2JGWnI0cW5xUUdDbUI4TS9tRVFHY0VmWWxZczJjWHEr?=
 =?utf-8?Q?8JQ86t2VefJOe4CEGwMPfq+MB?=
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On 2/7/2023 7:21 AM, Sean Christopherson wrote:
> Define the "physical table max index mask" as bits 8:0, not 9:0.  x2AVIC
> currently supports a max of 512 entries, i.e. the max index is 511, and
> the inputs to GENMASK_ULL() are inclusive.  The bug is benign as bit 9 is
> reserved and never set by KVM, i.e. KVM is just clearing bits that are
> guaranteed to be zero.
> 
> Note, as of this writing, APM "Rev. 3.39-October 2022" incorrectly states
> that bits 11:8 are reserved in Table B-1. VMCB Layout, Control Area.  I.e.
> that table wasn't updated when x2AVIC support was added.
> 
> Opportunistically fix the comment for the max AVIC ID to align with the
> code, and clean up comment formatting too.
> 
> Fixes: 4d1d7942e36a ("KVM: SVM: Introduce logic to (de)activate x2AVIC mode")
> Cc: stable@vger.kernel.org
> Cc: Alejandro Jimenez <alejandro.j.jimenez@oracle.com>
> Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> Signed-off-by: Sean Christopherson <seanjc@google.com>
> ---
>   arch/x86/include/asm/svm.h | 12 +++++++-----
>   1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h
> index cb1ee53ad3b1..770dcf75eaa9 100644
> --- a/arch/x86/include/asm/svm.h
> +++ b/arch/x86/include/asm/svm.h
> @@ -261,20 +261,22 @@ enum avic_ipi_failure_cause {
>   	AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
>   };
>   
> -#define AVIC_PHYSICAL_MAX_INDEX_MASK	GENMASK_ULL(9, 0)
> +#define AVIC_PHYSICAL_MAX_INDEX_MASK	GENMASK_ULL(8, 0)
>   
>   /*
> - * For AVIC, the max index allowed for physical APIC ID
> - * table is 0xff (255).
> + * For AVIC, the max index allowed for physical APIC ID table is 0xfe (254), as
> + * 0xff is a broadcast to all CPUs, i.e. can't be targeted individually.
>    */
>   #define AVIC_MAX_PHYSICAL_ID		0XFEULL
>   
>   /*
> - * For x2AVIC, the max index allowed for physical APIC ID
> - * table is 0x1ff (511).
> + * For x2AVIC, the max index allowed for physical APIC ID table is 0x1ff (511).
>    */
>   #define X2AVIC_MAX_PHYSICAL_ID		0x1FFUL
>   
> +static_assert((AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == AVIC_MAX_PHYSICAL_ID);
> +static_assert((X2AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == X2AVIC_MAX_PHYSICAL_ID);
> +
>   #define AVIC_HPA_MASK	~((0xFFFULL << 52) | 0xFFF)
>   #define VMCB_AVIC_APIC_BAR_MASK		0xFFFFFFFFFF000ULL
>   

Reviewed-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>

Thanks,
Suravee