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[131.111.5.143]) by smtp.gmail.com with ESMTPSA id d15-20020a5d6dcf000000b002c3f9404c45sm16991637wrz.7.2023.02.15.14.43.40 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 15 Feb 2023 14:43:41 -0800 (PST) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3696.120.41.1.1\)) Subject: Re: [PATCH v2 2/6] RISC-V: Add a syscall for HW probing From: Jessica Clarke In-Reply-To: Date: Wed, 15 Feb 2023 22:43:40 +0000 Cc: Arnd Bergmann , =?utf-8?Q?Heiko_St=C3=BCbner?= , linux-doc@vger.kernel.org, Andrew Bresticker , Atish Patra , Palmer Dabbelt , "Conor.Dooley" , Celeste Liu , slewis@rivosinc.com, Bagas Sanjaya , linux-riscv , Jonathan Corbet , Tobias Klauser , Andrew Jones , Albert Ou , Vineet Gupta , Dao Lu , Paul Walmsley , Ruizhe Pan , Anup Patel , Randy Dunlap , Linux Kernel Mailing List , Conor Dooley , Palmer Dabbelt , guoren Content-Transfer-Encoding: quoted-printable Message-Id: <6FA7F803-1B4A-418E-9368-E205F3A6CF27@jrtc27.com> References: <20230206201455.1790329-1-evan@rivosinc.com> <20230206201455.1790329-3-evan@rivosinc.com> To: Evan Green X-Mailer: Apple Mail (2.3696.120.41.1.1) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 15 Feb 2023, at 21:14, Evan Green wrote: >=20 > On Wed, Feb 15, 2023 at 1:57 AM Arnd Bergmann wrote: >>=20 >> On Mon, Feb 6, 2023, at 21:14, Evan Green wrote: >>> We don't have enough space for these all in ELF_HWCAP{,2} and = there's no >>> system call that quite does this, so let's just provide an = arch-specific >>> one to probe for hardware capabilities. This currently just = provides >>> m{arch,imp,vendor}id, but with the key-value pairs we can pass more = in >>> the future. >>>=20 >>> Co-developed-by: Palmer Dabbelt >>> Signed-off-by: Palmer Dabbelt >>> Signed-off-by: Evan Green >>=20 >> I'm not sure I understand the problem with >> AT_HWCAP. While the bits in AT_HWCAP and AT_HWCAP2 >> are limited, I don't see us running out of new >> AT_* words to use for additional bits. Presumably >> the kernel would already have to know about the >> name of each supported HW feature and could assign >> a unique bit number to them. >=20 > Palmer can probably speak to this with more authority, but my > understanding about the motivation for an approach like this goes > something like: > * With the nature of RISC-V, we expect a lot of these types of bits > and bobs, many more than we've seen with the likes of x86 and ARM. We=E2=80=99re already at (I think) 51 standard user-level extensions = that LLVM knows about. > * We also expect in some cases these values to be inconsistent across = CPUs. That=E2=80=99s also true of some Arm SoCs. > * While we could copy all that data into the aux vector every time, > it starts to look like a lot of data, not all programs care about all > of it, and a lot of it is static, making all the copying wasteful. Bitvectors are pretty cheap, this is negligible. > * Another option that would solve most of this would be to point to a > vDSO data area from the aux vector. This solves the copy complaints, > but makes that vDSO data ABI, and requires it all to be known up > front. That doesn't seem like a huge deal, other than my usual point of needing a standardised portable cross-platform API for this, so that shouldn=E2=80=99t be =E2=80=9Cthe=E2=80=9D generic interface programmed = against by applications. > * So, a syscall with a vDSO function in front of it seemed like a > good combination of speed and flexibility. >=20 > You're certainly right that HWCAPn would work for what we're exposing > today, so the question probably comes down to our relative predictions > of how this data will grow. The other big problem is vendor extensions. Jess > -Evan >=20 > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv