Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F61DC61DA4 for ; Thu, 16 Feb 2023 05:33:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229765AbjBPFdm (ORCPT ); Thu, 16 Feb 2023 00:33:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229558AbjBPFdj (ORCPT ); Thu, 16 Feb 2023 00:33:39 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44480B76D; Wed, 15 Feb 2023 21:33:37 -0800 (PST) X-UUID: 7281eb22adbb11eda06fc9ecc4dadd91-20230216 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=00ajyg9hyR5SZbFFofZ+uji6sO3so8wig2JChznc7sw=; b=RYmz79tj7k16Z73tuL6MyaerYkSxjrm8oamoA8BRMEK+PQtXH1TXL4alUr7lMqAMQB4tQ0VM2VBbjUXLaofvclmsLMibOgxVEVMpOXeI4/LgAPRIAcNAcZYrEtlXcEl65k2pGlEKkYV7bsUi8+QLy+O7m2TKKkVpvDQ93dVqlu8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.19,REQID:5d1c4428-2119-4c20-b0a1-3c13a0cfc49c,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:885ddb2,CLOUDID:cefa9bb0-beed-4dfc-bd9c-e1b22fa6ccc4,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-UUID: 7281eb22adbb11eda06fc9ecc4dadd91-20230216 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 196981102; Thu, 16 Feb 2023 13:33:30 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Thu, 16 Feb 2023 13:33:30 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 16 Feb 2023 13:33:29 +0800 From: Yong Wu To: Joerg Roedel , Will Deacon , Rob Herring , Matthias Brugger CC: Robin Murphy , Krzysztof Kozlowski , Yong Wu , AngeloGioacchino Del Regno , , , , , , , , , , Subject: [PATCH v7 0/6] MT8188 IOMMU SUPPORT Date: Thu, 16 Feb 2023 13:33:16 +0800 Message-ID: <20230216053322.11596-1-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org MT8188 have 3 IOMMU HWs. 2 IOMMU HW is for multimedia, and 1 IOMMU HW is for infra-master, like PCIe. About the 2 MM IOMMU HW, the connection could be something like this: IOMMU(VDO) IOMMU(VPP) | | SMI_COMMON(VDO) SMI_COMMON(VPP) --------------- ---------------- | | ... | | ... larb0 larb2 ... larb1 larb3 ... INFRA IOMMU does not have SMI, the master connects to IOMMU directly. Although multiple banks supported in MT8188, we only use one of them, which means PCIe is put in bank0 of INFRA IOMMU. So we have two pgtable for MT8188, specifically, these two MM IOMMU HW share a pgtable while INFRA IOMMU HW use a independent pgtable. Another change is that we add some SMC command for INFRA master to enable/disable INFRA IOMMU in ATF considering security concerns. We also adjust the flow of mtk_iommu_config to reduce indention. changes since v7: - Base on mtk-iommu-dma-range-v4: https://lore.kernel.org/linux-mediatek/20230215062544.8677-1-yong.wu@mediatek.com/ - Add a new patch for two IOMMU share pagetable issue. - Add a new patch for adding iova_region_larb_msk for mt8188. - Add the comment in the dt-binding header file about larb index. This is for readable when updating the iova_region_larb_msk. Since there is something wrong for chengci's mail account when sending to devicetree mail list, we don't know why. I help send this patchset. https://lore.kernel.org/linux-mediatek/5a916595-12ee-92e6-d380-84146dd75218@linaro.org/ changes since v6: https://lore.kernel.org/linux-mediatek/20221223101439.494-1-chengci.xu@mediatek.com/ - base on tag: next-20221220. - update commit message of patch[2/4]. changes since v5: - base on tag: next-20221205. - add flag PGTABLE_PA_35_EN for all IOMMU in MT8188. - modify the type of "portid_msk" from "u32" to "unsigned long". changes since v4: - base on tag: next-20221018. - add patch[2/4] to reduce indention by adjust mtk_iommu_config flow. changes since v3: - base on tag: next-20220916. - use license "GPL-2.0-only OR BSD-2-Clause" in bingings head file. - drop redundant "portid" assignment when configure infra master. - reduce indentation by using "else if" when config infra master. - update probe flow about "pericfg" for CFG_IFA_MASTER_IN_ATF. - drop unused "pericfg_comp_str" in mt8188_data_infra. - drop words like "This commit/patch". changes since v2: - base on tag: next-20220831. - rename "mt8188-memory-port.h" to "mediatek,mt8188-memory-port.h". - use dual-license in "mediatek,mt8188-memory-port.h" - remove unnecessary "()" when define SMI_LARB_ID changes since v1: - base on tag: next-20220803. - adds MT8188 IOMMU support. Chengci.Xu (5): dt-bindings: mediatek: mt8188: Add binding for MM & INFRA IOMMU iommu/mediatek: Fix two IOMMU share pagetable issue iommu/mediatek: Adjust mtk_iommu_config flow iommu/mediatek: Add enable IOMMU SMC command for INFRA master iommu/mediatek: Add MT8188 IOMMU Support Yong Wu (1): iommu/mediatek: mt8188: Add iova_region_larb_msk .../bindings/iommu/mediatek,iommu.yaml | 12 +- drivers/iommu/mtk_iommu.c | 151 ++++-- .../memory/mediatek,mt8188-memory-port.h | 489 ++++++++++++++++++ include/soc/mediatek/smi.h | 1 + 4 files changed, 621 insertions(+), 32 deletions(-) create mode 100644 include/dt-bindings/memory/mediatek,mt8188-memory-port.h -- 2.18.0