Message-ID: <48c4b1f81c21950e9fd46d4acb5196d979b147cb.camel@xry111.site>
Subject: Re: [PATCH v4 2/5] LoongArch: Use la.pcrel instead of la.abs for
 exception handlers
From:   Xi Ruoyao <xry111@xry111.site>
To:     Jinyang He <hejinyang@loongson.cn>,
        Youling Tang <tangyouling@loongson.cn>,
        Huacai Chen <chenhuacai@kernel.org>
Cc:     Xuerui Wang <kernel@xen0n.name>, loongarch@lists.linux.dev,
        linux-kernel@vger.kernel.org, Xuefeng Li <lixuefeng@loongson.cn>,
        Jianmin lv <lvjianmin@loongson.cn>,
        Tiezhu Yang <yangtiezhu@loongson.cn>
Date:   Thu, 16 Feb 2023 15:10:17 +0800
In-Reply-To: <5adf0fc4-b75c-f7f2-311c-0f5d8f14311b@loongson.cn>
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         <CAAhV-H4Bs5n_ek3mq6zwxAgVw0nvER1XUA+WUA8M12eKcYVPDQ@mail.gmail.com>
         <05ef2d91-ab87-b8d9-85fa-6a90a92f8f39@loongson.cn>
         <848e2985-9ba3-c14d-23ac-a7f1c218215f@loongson.cn>
         <5adf0fc4-b75c-f7f2-311c-0f5d8f14311b@loongson.cn>
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On Thu, 2023-02-16 at 14:59 +0800, Jinyang He wrote:
> +.macro la.abs reg, sym
> +766:
> +=C2=A0=C2=A0=C2=A0 nop
> +=C2=A0=C2=A0=C2=A0 nop
> +=C2=A0=C2=A0=C2=A0 nop
> +=C2=A0=C2=A0=C2=A0 nop

In the "formal" version we can code

lu12i.w		reg, 0
ori		reg, reg, 0
lu32i.d		reg, 0
lu52i.d		reg, reg, 0

here.  Then we only need to fixup the immediate slot so we can avoid
using parse_r.


> +=C2=A0=C2=A0=C2=A0 .pushsection ".laabs", "aw", %progbits
> +768:
> +=C2=A0=C2=A0=C2=A0 .word 768b-766b
> +=C2=A0=C2=A0=C2=A0 parse_r regno, \reg
> +=C2=A0=C2=A0=C2=A0 .word regno
> +=C2=A0=C2=A0=C2=A0 .dword \sym
> +=C2=A0=C2=A0=C2=A0 .popsection
> +.endm

--=20
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University