From:   Colin Foster <colin.foster@in-advantage.com>
To:     linux-phy@lists.infradead.org, netdev@vger.kernel.org,
        linux-kernel@vger.kernel.org
Cc:     Russell King <linux@armlinux.org.uk>,
        Kishon Vijay Abraham I <kishon@kernel.org>,
        Vinod Koul <vkoul@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Eric Dumazet <edumazet@google.com>,
        "David S. Miller" <davem@davemloft.net>,
        Florian Fainelli <f.fainelli@gmail.com>,
        Andrew Lunn <andrew@lunn.ch>, UNGLinuxDriver@microchip.com,
        Alexandre Belloni <alexandre.belloni@bootlin.com>,
        Claudiu Manoil <claudiu.manoil@nxp.com>,
        Vladimir Oltean <vladimir.oltean@nxp.com>,
        Lee Jones <lee@kernel.org>
Subject: [RFC v1 net-next 0/7] add support for ocelot external ports
Date:   Wed, 15 Feb 2023 23:53:14 -0800
Message-Id: <20230216075321.2898003-1-colin.foster@in-advantage.com>
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This is the start of part 3 of what is hopefully a 3-part series to add
Ethernet switching support to Ocelot chips.

Part 1 of the series (A New Chip) added general support for Ocelot chips
that were controlled externally via SPI.
https://lore.kernel.org/all/20220815005553.1450359-1-colin.foster@in-advantage.com/

Part 2 of the series (The Ethernet Strikes Back) added DSA Ethernet
support for ports 0-3, which are the four copper ports that are internal
to the chip.
https://lore.kernel.org/all/20230127193559.1001051-1-colin.foster@in-advantage.com/

Part 3 will, at a minimum, add support for ports 4-7, which are
configured to use QSGMII to an external phy (Return Of The QSGMII). With
any luck, and some guidance, support for SGMII, SFPs, etc. will also be
part of this series.


This patch series is absolutely an RFC at this point. While all 8 copper
ports on the VSC7512 are currently functional, I recognize there are a
couple empty function callbacks in the last patch that likely need to be
implemented.

Aside from that, there is feedback I'd greatly appreciate. Specifically
patch 6 ("net: dsa: felix: allow external parsing of port nodes") and
whether that is an acceptable way to solve the problem at hand.

Also, with patch 7 ("net: dsa: ocelot_ext: add support for external phys")
my basis was the function mscc_ocelot_init_ports(), but there were several
changes I had to make for DSA / Phylink. Are my implementations of
ocelot_ext_parse_port_node() and ocelot_ext_phylink_create() barking up
the right tree?


For reference, a boot log in case it is useful:

[    3.222208] pinctrl-ocelot ocelot-pinctrl.0.auto: DMA mask not set
[    3.231781] pinctrl-ocelot ocelot-pinctrl.0.auto: driver registered
[    3.241747] pinctrl-microchip-sgpio ocelot-sgpio.1.auto: DMA mask not set
[    3.260366] mscc-miim ocelot-miim0.2.auto: DMA mask not set
[    3.787309] mscc-miim ocelot-miim1.3.auto: DMA mask not set
[    3.822367] mscc,ocelot-serdes ocelot-serdes.4.auto: DMA mask not set
[    3.837637] ocelot-switch ocelot-switch.5.auto: DMA mask not set
[    5.368119] ocelot-switch ocelot-switch.5.auto: PHY [ocelot-miim1.3.auto-mii:04] driver [Microsemi GE VSC8514 SyncE] (irq=POLL)
[    5.668093] ocelot-switch ocelot-switch.5.auto: PHY [ocelot-miim1.3.auto-mii:05] driver [Microsemi GE VSC8514 SyncE] (irq=POLL)
[    5.968342] ocelot-switch ocelot-switch.5.auto: PHY [ocelot-miim1.3.auto-mii:06] driver [Microsemi GE VSC8514 SyncE] (irq=POLL)
[    6.288098] ocelot-switch ocelot-switch.5.auto: PHY [ocelot-miim1.3.auto-mii:07] driver [Microsemi GE VSC8514 SyncE] (irq=POLL)
[    6.364114] ocelot-switch ocelot-switch.5.auto: PHY [ocelot-miim0.2.auto-mii:00] driver [Generic PHY] (irq=POLL)
[    6.375061] ocelot-switch ocelot-switch.5.auto: configuring for phy/internal link mode
[    6.391843] ocelot-switch ocelot-switch.5.auto swp1 (uninitialized): PHY [ocelot-miim0.2.auto-mii:01] driver [Generic PHY] (irq=POLL)
[    6.410033] ocelot-switch ocelot-switch.5.auto swp2 (uninitialized): PHY [ocelot-miim0.2.auto-mii:02] driver [Generic PHY] (irq=POLL)
[    6.427761] ocelot-switch ocelot-switch.5.auto swp3 (uninitialized): PHY [ocelot-miim0.2.auto-mii:03] driver [Generic PHY] (irq=POLL)
[    6.598305] ocelot-switch ocelot-switch.5.auto swp4 (uninitialized): PHY [ocelot-miim1.3.auto-mii:04] driver [Microsemi GE VSC8514 SyncE] (irq=POLL)
[    6.778331] ocelot-switch ocelot-switch.5.auto swp5 (uninitialized): PHY [ocelot-miim1.3.auto-mii:05] driver [Microsemi GE VSC8514 SyncE] (irq=POLL)
[    6.958337] ocelot-switch ocelot-switch.5.auto swp6 (uninitialized): PHY [ocelot-miim1.3.auto-mii:06] driver [Microsemi GE VSC8514 SyncE] (irq=POLL)
[    7.138379] ocelot-switch ocelot-switch.5.auto swp7 (uninitialized): PHY [ocelot-miim1.3.auto-mii:07] driver [Microsemi GE VSC8514 SyncE] (irq=POLL)
[    7.156375] device eth0 entered promiscuous mode
[    7.161140] DSA: tree 0 setup


And a couple device tree snippets of the ports:

&spi0 {
        #address-cells = <1>;
        #size-cells = <0>;
        status = "okay";

        soc@0 {
                compatible = "mscc,vsc7512";
                spi-max-frequency = <2500000>;
                reg = <0 0>;
                #address-cells = <1>;
                #size-cells = <1>;

                ethernet-switch@71010000 {
                        compatible = "mscc,vsc7512-switch";
                        ...

                        ports {
                                ...
                                port@4 {
                                       reg = <4>;
                                       label = "swp4";
                                       status = "okay";
                                       phy-handle = <&sw_phy4>;
                                       phy-mode = "qsgmii";
                                       phys = <&serdes 4 SERDES6G(0)>;
                               };
                               ...
                        };
                        ...
                };

                mdio@710700c0 {
                        compatible = "mscc,ocelot-miim";
                        pinctrl-names = "default";
                        pinctrl-0 = <&miim1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0x710700c0 0x24>;

                        sw_phy4: ethernet-phy@4 {
                                reg = <0x4>;
                        };
                        ...
                };
                ...

                serdes: serdes {
                        compatible = "mscc,vsc7514-serdes";
                        #phy-cells = <2>;
                };
        };
};


Colin Foster (7):
  phy: phy-ocelot-serdes: add ability to be used in a non-syscon
    configuration
  mfd: ocelot: add ocelot-serdes capability
  net: mscc: ocelot: expose ocelot_pll5_init routine
  net: mscc: ocelot: expose generic phylink_mac_config routine
  net: dsa: felix: attempt to initialize internal hsio plls
  net: dsa: felix: allow external parsing of port nodes
  net: dsa: ocelot_ext: add support for external phys

 drivers/mfd/ocelot-core.c                  |  13 +
 drivers/net/dsa/ocelot/felix.c             |  57 +++-
 drivers/net/dsa/ocelot/felix.h             |   6 +
 drivers/net/dsa/ocelot/ocelot_ext.c        | 319 ++++++++++++++++++++-
 drivers/net/ethernet/mscc/ocelot.c         |  57 ++++
 drivers/net/ethernet/mscc/ocelot_net.c     |  21 +-
 drivers/net/ethernet/mscc/ocelot_vsc7514.c |  30 --
 drivers/phy/mscc/phy-ocelot-serdes.c       |   9 +
 include/soc/mscc/ocelot.h                  |   5 +
 9 files changed, 440 insertions(+), 77 deletions(-)

-- 
2.25.1