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References: <20230214134127.59273-1-angelogioacchino.delregno@collabora.com> <20230214134127.59273-12-angelogioacchino.delregno@collabora.com>
In-Reply-To: <20230214134127.59273-12-angelogioacchino.delregno@collabora.com>
From:   Chen-Yu Tsai <wenst@chromium.org>
Date:   Thu, 16 Feb 2023 15:54:23 +0800
Message-ID: <CAGXv+5HpWTTqrFKhkUDoZWa4h1wm=OuDHgFyMQsL-C4xKVfqOg@mail.gmail.com>
Subject: Re: [PATCH v2 11/47] clk: mediatek: mt8365: Convert simple_gate to
 mtk_gate clocks
To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
Cc:     mturquette@baylibre.com, sboyd@kernel.org, matthias.bgg@gmail.com,
        johnson.wang@mediatek.com, miles.chen@mediatek.com,
        chun-jie.chen@mediatek.com, daniel@makrotopia.org,
        fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com,
        rex-bc.chen@mediatek.com, zhaojh329@gmail.com,
        sam.shih@mediatek.com, edward-jw.yang@mediatek.com,
        yangyingliang@huawei.com, granquet@baylibre.com,
        pablo.sun@mediatek.com, sean.wang@mediatek.com,
        chen.zhong@mediatek.com, linux-kernel@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org, kernel@collabora.com
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On Tue, Feb 14, 2023 at 9:41 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> On this SoC some clocks apparently don't have different offsets for
> set/clr/sta registers hence they can be set, cleared and status-read
> on one register: this means that it was possible to use simpler gate
> clocks instead of custom mtk_gate ones.
>
> In preparation for converting this clock driver to the common probe
> mechanism for MediaTek clocks, perform a conversion from simple_gate
> to mtk_gate clocks since the latter does provide implicit support
> for simple gate clocks as well.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>