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[83.9.1.117]) by smtp.gmail.com with ESMTPSA id x20-20020a2e9dd4000000b00292b759af81sm140835ljj.92.2023.02.16.02.43.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 Feb 2023 02:43:14 -0800 (PST) Message-ID: <77c66b89-ff06-3440-380f-4ef8046b945c@linaro.org> Date: Thu, 16 Feb 2023 11:43:12 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.2 Subject: Re: [PATCH 2/7] clk: qcom: gcc-ipq4019: convert XO and sleep clk to parent_data Content-Language: en-US From: Konrad Dybcio To: Robert Marko , andersson@kernel.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: luka.perkov@sartura.hr References: <20230214162325.312057-1-robert.marko@sartura.hr> <20230214162325.312057-2-robert.marko@sartura.hr> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16.02.2023 11:42, Konrad Dybcio wrote: > > > On 14.02.2023 17:23, Robert Marko wrote: >> Start off IPQ4019 GCC conversion by converting XO and sleep clks to >> parent data in order to directly pass them. >> >> Signed-off-by: Robert Marko >> --- > Reviewed-by: Konrad Dybcio > > Konrad Actually, any reason not to use .index? Konrad >> drivers/clk/qcom/gcc-ipq4019.c | 75 ++++++++++++++++++++-------------- >> 1 file changed, 45 insertions(+), 30 deletions(-) >> >> diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c >> index 362c732536cd3..a50887d3626f7 100644 >> --- a/drivers/clk/qcom/gcc-ipq4019.c >> +++ b/drivers/clk/qcom/gcc-ipq4019.c >> @@ -657,8 +657,9 @@ static struct clk_branch gcc_dcd_xo_clk = { >> .enable_mask = BIT(0), >> .hw.init = &(struct clk_init_data){ >> .name = "gcc_dcd_xo_clk", >> - .parent_names = (const char *[]){ >> - "xo", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "xo", >> + .name = "xo", >> }, >> .num_parents = 1, >> .ops = &clk_branch2_ops, >> @@ -954,8 +955,9 @@ static struct clk_branch gcc_usb2_sleep_clk = { >> .enable_mask = BIT(0), >> .hw.init = &(struct clk_init_data){ >> .name = "gcc_usb2_sleep_clk", >> - .parent_names = (const char *[]){ >> - "gcc_sleep_clk_src", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "sleep_clk", >> + .name = "gcc_sleep_clk_src", >> }, >> .num_parents = 1, >> .ops = &clk_branch2_ops, >> @@ -1021,8 +1023,9 @@ static struct clk_branch gcc_usb3_sleep_clk = { >> .enable_mask = BIT(0), >> .hw.init = &(struct clk_init_data){ >> .name = "gcc_usb3_sleep_clk", >> - .parent_names = (const char *[]){ >> - "gcc_sleep_clk_src", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "sleep_clk", >> + .name = "gcc_sleep_clk_src", >> }, >> .num_parents = 1, >> .ops = &clk_branch2_ops, >> @@ -1110,8 +1113,9 @@ static struct clk_branch gcc_wcss2g_ref_clk = { >> .enable_mask = BIT(0), >> .hw.init = &(struct clk_init_data){ >> .name = "gcc_wcss2g_ref_clk", >> - .parent_names = (const char *[]){ >> - "xo", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "xo", >> + .name = "xo", >> }, >> .num_parents = 1, >> .ops = &clk_branch2_ops, >> @@ -1127,8 +1131,9 @@ static struct clk_branch gcc_wcss2g_rtc_clk = { >> .enable_mask = BIT(0), >> .hw.init = &(struct clk_init_data){ >> .name = "gcc_wcss2g_rtc_clk", >> - .parent_names = (const char *[]){ >> - "gcc_sleep_clk_src", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "sleep_clk", >> + .name = "gcc_sleep_clk_src", >> }, >> .num_parents = 1, >> .ops = &clk_branch2_ops, >> @@ -1179,8 +1184,9 @@ static struct clk_branch gcc_wcss5g_ref_clk = { >> .enable_mask = BIT(0), >> .hw.init = &(struct clk_init_data){ >> .name = "gcc_wcss5g_ref_clk", >> - .parent_names = (const char *[]){ >> - "xo", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "xo", >> + .name = "xo", >> }, >> .num_parents = 1, >> .ops = &clk_branch2_ops, >> @@ -1196,8 +1202,9 @@ static struct clk_branch gcc_wcss5g_rtc_clk = { >> .enable_mask = BIT(0), >> .hw.init = &(struct clk_init_data){ >> .name = "gcc_wcss5g_rtc_clk", >> - .parent_names = (const char *[]){ >> - "gcc_sleep_clk_src", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "sleep_clk", >> + .name = "gcc_sleep_clk_src", >> }, >> .num_parents = 1, >> .ops = &clk_branch2_ops, >> @@ -1360,8 +1367,9 @@ static struct clk_fepll gcc_apss_cpu_plldiv_clk = { >> .enable_mask = BIT(0), >> .hw.init = &(struct clk_init_data){ >> .name = "ddrpllapss", >> - .parent_names = (const char *[]){ >> - "xo", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "xo", >> + .name = "xo", >> }, >> .num_parents = 1, >> .ops = &clk_regmap_cpu_div_ops, >> @@ -1412,8 +1420,9 @@ static struct clk_fepll gcc_apss_sdcc_clk = { >> .cdiv.clkr = { >> .hw.init = &(struct clk_init_data){ >> .name = "ddrpllsdcc", >> - .parent_names = (const char *[]){ >> - "xo", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "xo", >> + .name = "xo", >> }, >> .num_parents = 1, >> .ops = &clk_fepll_div_ops, >> @@ -1427,8 +1436,9 @@ static struct clk_fepll gcc_fepll125_clk = { >> .cdiv.clkr = { >> .hw.init = &(struct clk_init_data){ >> .name = "fepll125", >> - .parent_names = (const char *[]){ >> - "xo", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "xo", >> + .name = "xo", >> }, >> .num_parents = 1, >> .ops = &clk_fepll_div_ops, >> @@ -1442,8 +1452,9 @@ static struct clk_fepll gcc_fepll125dly_clk = { >> .cdiv.clkr = { >> .hw.init = &(struct clk_init_data){ >> .name = "fepll125dly", >> - .parent_names = (const char *[]){ >> - "xo", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "xo", >> + .name = "xo", >> }, >> .num_parents = 1, >> .ops = &clk_fepll_div_ops, >> @@ -1457,8 +1468,9 @@ static struct clk_fepll gcc_fepll200_clk = { >> .cdiv.clkr = { >> .hw.init = &(struct clk_init_data){ >> .name = "fepll200", >> - .parent_names = (const char *[]){ >> - "xo", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "xo", >> + .name = "xo", >> }, >> .num_parents = 1, >> .ops = &clk_fepll_div_ops, >> @@ -1472,8 +1484,9 @@ static struct clk_fepll gcc_fepll500_clk = { >> .cdiv.clkr = { >> .hw.init = &(struct clk_init_data){ >> .name = "fepll500", >> - .parent_names = (const char *[]){ >> - "xo", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "xo", >> + .name = "xo", >> }, >> .num_parents = 1, >> .ops = &clk_fepll_div_ops, >> @@ -1497,8 +1510,9 @@ static struct clk_fepll gcc_fepllwcss2g_clk = { >> .cdiv.clkr = { >> .hw.init = &(struct clk_init_data){ >> .name = "fepllwcss2g", >> - .parent_names = (const char *[]){ >> - "xo", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "xo", >> + .name = "xo", >> }, >> .num_parents = 1, >> .ops = &clk_fepll_div_ops, >> @@ -1515,8 +1529,9 @@ static struct clk_fepll gcc_fepllwcss5g_clk = { >> .cdiv.clkr = { >> .hw.init = &(struct clk_init_data){ >> .name = "fepllwcss5g", >> - .parent_names = (const char *[]){ >> - "xo", >> + .parent_data = &(const struct clk_parent_data){ >> + .fw_name = "xo", >> + .name = "xo", >> }, >> .num_parents = 1, >> .ops = &clk_fepll_div_ops,