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X-MS-Exchange-CrossTenant-Network-Message-Id: 88fe2f0a-c5df-460a-3339-08db10c0977b X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Feb 2023 08:25:56.4099 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: wN8KqyZd0c0OG37ti1FH4h4eFwrbBBWxLFeXEFWAvXMeeLGn1gagI0cT4OjNknwFIq0IcgTRncestp3P01SYkQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR18MB3565 X-Proofpoint-ORIG-GUID: ReM--AVlQ-5pE0WXKg8kHb6OvDXO3Ibq X-Proofpoint-GUID: ReM--AVlQ-5pE0WXKg8kHb6OvDXO3Ibq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-17_04,2023-02-16_01,2023-02-09_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Maciej Fijalkowski > Sent: Tuesday, February 14, 2023 9:43 AM > To: Veerasenareddy Burru > Cc: netdev@vger.kernel.org; linux-kernel@vger.kernel.org; Abhijit Ayareka= r > ; Sathesh B Edara ; > Satananda Burla ; linux-doc@vger.kernel.org; David S. > Miller ; Eric Dumazet ; > Jakub Kicinski ; Paolo Abeni > Subject: [EXT] Re: [PATCH net-next v3 2/7] octeon_ep: poll for control > messages >=20 > External Email >=20 > ---------------------------------------------------------------------- > On Mon, Feb 13, 2023 at 09:14:17PM -0800, Veerasenareddy Burru wrote: > > Poll for control messages until interrupts are enabled. > > All the interrupts are enabled in ndo_open(). > > Add ability to listen for notifications from firmware before ndo_open()= . > > Once interrupts are enabled, this polling is disabled and all the > > messages are processed by bottom half of interrupt handler. > > > > Signed-off-by: Veerasenareddy Burru > > Signed-off-by: Abhijit Ayarekar >=20 > small two nits >=20 > > --- > > v2-> v3: > > * resovled review comment; fixed reverse christmas tree. > > > > v1 -> v2: > > * removed device status oct->status, as it is not required with the > > modified implementation in 0001-xxxx.patch > > > > .../marvell/octeon_ep/octep_cn9k_pf.c | 49 +++++++++---------- > > .../ethernet/marvell/octeon_ep/octep_main.c | 35 +++++++++++++ > > .../ethernet/marvell/octeon_ep/octep_main.h | 11 ++++- > > .../marvell/octeon_ep/octep_regs_cn9k_pf.h | 4 ++ > > 4 files changed, 71 insertions(+), 28 deletions(-) > > > > diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c > > b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c > > index 6ad88d0fe43f..f40ebac15a79 100644 > > --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c > > +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c > > @@ -352,27 +352,36 @@ static void > octep_setup_mbox_regs_cn93_pf(struct octep_device *oct, int q_no) > > mbox->mbox_read_reg =3D oct->mmio[0].hw_addr + > > CN93_SDP_R_MBOX_VF_PF_DATA(q_no); } > > > > -/* Mailbox Interrupt handler */ > > -static void cn93_handle_pf_mbox_intr(struct octep_device *oct) > > +/* Process non-ioq interrupts required to keep pf interface running. > > + * OEI_RINT is needed for control mailbox */ static int > > +octep_poll_non_ioq_interrupts_cn93_pf(struct octep_device *oct) >=20 > return bool? >=20 Yes, bool is sufficient. Will make the change in next revision. > > { > > - u64 mbox_int_val =3D 0ULL, val =3D 0ULL, qno =3D 0ULL; > > + int handled =3D 0; > > + u64 reg0; > > > > - mbox_int_val =3D readq(oct->mbox[0]->mbox_int_reg); > > - for (qno =3D 0; qno < OCTEP_MAX_VF; qno++) { > > - val =3D readq(oct->mbox[qno]->mbox_read_reg); > > - dev_dbg(&oct->pdev->dev, > > - "PF MBOX READ: val:%llx from VF:%llx\n", val, qno); > > + /* Check for OEI INTR */ > > + reg0 =3D octep_read_csr64(oct, CN93_SDP_EPF_OEI_RINT); > > + if (reg0) { > > + dev_info(&oct->pdev->dev, > > + "Received OEI_RINT intr: 0x%llx\n", > > + reg0); > > + octep_write_csr64(oct, CN93_SDP_EPF_OEI_RINT, reg0); > > + if (reg0 & CN93_SDP_EPF_OEI_RINT_DATA_BIT_MBOX) > > + queue_work(octep_wq, &oct->ctrl_mbox_task); > > + > > + handled =3D 1; > > } > > > > - writeq(mbox_int_val, oct->mbox[0]->mbox_int_reg); > > + return handled; > > } > > > > /* Interrupts handler for all non-queue generic interrupts. */ > > static irqreturn_t octep_non_ioq_intr_handler_cn93_pf(void *dev) { > > struct octep_device *oct =3D (struct octep_device *)dev; > > - struct pci_dev *pdev =3D oct->pdev; > > u64 reg_val =3D 0; > > + struct pci_dev *pdev =3D oct->pdev; >=20 > why this move of var and rct breakage? >=20 Thank you for the feedback. This change was not necessary. Will revert this= change. I will recheck whole patchset for RCT breakage and fix it in next revision. > > int i =3D 0; > > > > /* Check for IRERR INTR */ > > @@ -434,24 +443,9 @@ static irqreturn_t > octep_non_ioq_intr_handler_cn93_pf(void *dev) > > goto irq_handled; > > } > > > > - /* Check for MBOX INTR */ > > - reg_val =3D octep_read_csr64(oct, CN93_SDP_EPF_MBOX_RINT(0)); > > - if (reg_val) { > > - dev_info(&pdev->dev, > > - "Received MBOX_RINT intr: 0x%llx\n", reg_val); > > - cn93_handle_pf_mbox_intr(oct); > > + /* Check for MBOX INTR and OEI INTR */ > > + if (octep_poll_non_ioq_interrupts_cn93_pf(oct)) > > goto irq_handled; > > - } > > - > > - /* Check for OEI INTR */ > > - reg_val =3D octep_read_csr64(oct, CN93_SDP_EPF_OEI_RINT); > > - if (reg_val) { > > - dev_info(&pdev->dev, > > - "Received OEI_EINT intr: 0x%llx\n", reg_val); > > - octep_write_csr64(oct, CN93_SDP_EPF_OEI_RINT, reg_val); > > - queue_work(octep_wq, &oct->ctrl_mbox_task); > > - goto irq_handled; > > - } > > > > /* Check for DMA INTR */ > > reg_val =3D octep_read_csr64(oct, CN93_SDP_EPF_DMA_RINT); > > @@ -712,6 +706,7 @@ void octep_device_setup_cn93_pf(struct > octep_device *oct) > > > > oct->hw_ops.enable_interrupts =3D > octep_enable_interrupts_cn93_pf; > > oct->hw_ops.disable_interrupts =3D > octep_disable_interrupts_cn93_pf; > > + oct->hw_ops.poll_non_ioq_interrupts =3D > octep_poll_non_ioq_interrupts_cn93_pf; > > > > oct->hw_ops.update_iq_read_idx =3D > octep_update_iq_read_index_cn93_pf;