Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F4CEC636D7 for ; Fri, 17 Feb 2023 10:12:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229773AbjBQKMT (ORCPT ); Fri, 17 Feb 2023 05:12:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229534AbjBQKMR (ORCPT ); Fri, 17 Feb 2023 05:12:17 -0500 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85E13627E4; Fri, 17 Feb 2023 02:12:16 -0800 (PST) Received: by mail-ed1-x52b.google.com with SMTP id ez12so2353315edb.1; Fri, 17 Feb 2023 02:12:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=7hw648BlWiWtBk/f0KKzoPuGmE7KbLFt/y3M1QgpRb8=; b=DkGgz7LrrshUUqf98FEQHx+4ZLsw1fmj5xlLMYyg/apRAjsxEw7p1q2hYhewpY//AC JgOSPxlI58u/6CrB5nHfIey6F8vFzD+IG3h1qtADCX3oNJnQ9VuURgFNHi9tc2KKhQ3Y T7cRhAo/RxwKzzcpWDvHV4kJRYaTe3ZU5R4DFUcINE8j4tEYgcDBxmVD9MAKeJayMoFL s+cpWPIhjOUCWh+HZPwXIWgujNEJrGjyWRFZLc2Ph8F+9Tj2N54bsdJ4+9gbMYFO5+ME ZMjzQcSSj5F3MJtyWzD6nHA/Vj/ff9wONV3GbAUHv9o3HdcwAF1IQ1JX6zFdJsQ/hGcZ iU6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=7hw648BlWiWtBk/f0KKzoPuGmE7KbLFt/y3M1QgpRb8=; b=BLFx10LkRaBafgzqD6uyLL8qh0YZB8e41yxP621iZVpvHK9m8J1H61SloIK8ztQWiF h8OFtYQTQlZia34h3SdT1VxLwV7I2jmo5+g17Koj0OEOdAK1iQqAXepAlS4Zo6kS9rxJ PlLUrql1HMsDefAyjy7niEgQUsHFHqSulKPbhvAvsZ8MShVG7KSmUgeSGcqv233oIwwx peDCRDbVxZnR2YHYmAnSTkepIK0ufJrUl1edp6fcgmhxf8NA1Kvw5ze+MhCAANHTH9ws 58W7bcUJ5nadH3aZ92BKlUj8gilfCTebPjr2tlj3liGR02oP7Dyzj/cMOR4BM7A+7oBn Y27w== X-Gm-Message-State: AO0yUKXM8105Az32Bw2C0tMqgy3hp13nzK6VQjG8rScWrK4kD1HOx6hC XS35pO5PzxllvzCE8/LEDmLddvVxIIU+4enbDE8= X-Google-Smtp-Source: AK7set+GT0Ah3I/6vPnxNmj3RSo2G/EDRSHCWkFAtQuG+sMISDYexJpAIhdh9LnTy7Wf3Mb443eJzI2NRdM6y6KK2Zo= X-Received: by 2002:a17:907:76ad:b0:8b1:749f:b2c6 with SMTP id jw13-20020a17090776ad00b008b1749fb2c6mr1849103ejc.2.1676628734827; Fri, 17 Feb 2023 02:12:14 -0800 (PST) MIME-Version: 1.0 References: <23068d0c-d37c-0563-e1c1-e4d112059f5b@linaro.org> <49c8255e-66f3-fa1f-2949-1f03f77a0fa4@linaro.org> <4dcaaa70-11e0-fc9d-da03-224d34e36983@linaro.org> In-Reply-To: <4dcaaa70-11e0-fc9d-da03-224d34e36983@linaro.org> From: Binbin Zhou Date: Fri, 17 Feb 2023 18:12:01 +0800 Message-ID: Subject: Re: [PATCH V2 1/2] dt-bindings: interrupt-controller: Add Loongson EIOINTC To: Krzysztof Kozlowski Cc: Binbin Zhou , Huacai Chen , Jiaxun Yang , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Jianmin Lv , Huacai Chen , linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, loongarch@lists.linux.dev, devicetree@vger.kernel.org, loongson-kernel@lists.loongnix.cn Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Feb 17, 2023 at 4:40 PM Krzysztof Kozlowski wrote: > > On 17/02/2023 07:09, Binbin Zhou wrote: > > >>> Hi Krzysztof: > >>> > >>> Allow me to give a brief overview of the current status of eiointc (DT-based): > >>> Loongson-3A series supports eiointc; > >>> Loongson-2K1000 does not support eiointc now; > >>> Loongson-2K0500 supports eiointc, with differences from > >>> Loongson-3, e.g. only up to 128 devices are supported; > >>> Loongson-2K2000 supports eiointc, similar to Loongson-3. > >>> .... > >>> > >>> As can be seen, there is now a bit of confusion in the chip's design of eiointc. > >>> > >>> The design of eiointc is probably refined step by step with the chip. > >>> The same version of eiointc can be used for multiple chips, and the > >>> same chip series may also use different versions of eiointc. Low-end > >>> chips may use eiointc-2.0, and high-end chips may use eiointc-1.0, > >>> depending on the time it's produced. > >>> > >>> So in the Loongson-2K series I have defined the current state as > >>> eiointc-1.0, using the dts property to indicate the maximum number of > >>> devices supported by eiointc that can be used directly in the driver. > >>> > >>> If there are new changes to the design later on, such as the > >>> definition of registers, we can call it eiointc-2.0, which can also > >>> cover more than one chip. > >> > >> Just go with SoC-based compatibles. If your version is not specific > >> enough, then it is not a good way to represent the hardware. > >> > > > > Hi Krzysztof: > > > > I have tried to write the following SoC-based compatibles, is it fine? > > > > compatible: > > enum: > > - loongson,ls3a-eiointc # For MIPS Loongson-3A if necessary. > > - loongson,ls2k0500-eiointc > > - loongson,ls2k200-eiointc > > Looks good, but didn't you state these are compatible between each > other? I have impression there is a common set, so maybe one compatible > work on other device with reduced number of devices? > So far, the difference between ls2k SOCs is the number of devices supported by eiointc. Do you mean use unified compatible and reuse loongson,eio-num-vecs? Would this be possible, e.g. compatible: const: loongson,ls2k-eiointc loongson,eio-num-vecs: description: The number of devices supported by the extended I/O interrupt vector. $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1 maximum: 256 Thanks. Binbin > Best regards, > Krzysztof >