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X-MS-Exchange-CrossTenant-AuthSource: BYAPR18MB2423.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: bb663f32-a8a6-49fb-a65d-08db110a9607 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Feb 2023 17:15:36.7173 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: S2LosgD21Lzvzc3Y5WP7RDyboXjzGtE+kEPuMwMd8OyHW8q52BPKwJalzwdVIWV5ZQAYzLsIt6TJu60OAzLPjA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR18MB4900 X-Proofpoint-ORIG-GUID: EE4O8sev3baex1D1DptlNmefT0q2j76x X-Proofpoint-GUID: EE4O8sev3baex1D1DptlNmefT0q2j76x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-17_12,2023-02-17_01,2023-02-09_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Maciej Fijalkowski > Sent: Tuesday, February 14, 2023 9:49 AM > To: Veerasenareddy Burru > Cc: netdev@vger.kernel.org; linux-kernel@vger.kernel.org; Abhijit Ayareka= r > ; Sathesh B Edara ; > Satananda Burla ; linux-doc@vger.kernel.org; David S. > Miller ; Eric Dumazet ; > Jakub Kicinski ; Paolo Abeni > Subject: [EXT] Re: [PATCH net-next v3 3/7] octeon_ep: control mailbox for > multiple PFs >=20 > External Email >=20 > ---------------------------------------------------------------------- > On Mon, Feb 13, 2023 at 09:14:18PM -0800, Veerasenareddy Burru wrote: > > Add control mailbox support for multiple PFs. > > Update control mbox base address calculation based on PF function link. > > > > Signed-off-by: Veerasenareddy Burru > > Signed-off-by: Abhijit Ayarekar > > --- > > v2 -> v3: > > * no change > > > > v1 -> v2: > > * no change > > > > .../ethernet/marvell/octeon_ep/octep_cn9k_pf.c | 16 > +++++++++++++++- > > 1 file changed, 15 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c > > b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c > > index f40ebac15a79..c82a1347eed8 100644 > > --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c > > +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c > > @@ -13,6 +13,9 @@ > > #include "octep_main.h" > > #include "octep_regs_cn9k_pf.h" > > > > +#define CTRL_MBOX_MAX_PF 128 > > +#define CTRL_MBOX_SZ ((size_t)(0x400000 / > CTRL_MBOX_MAX_PF)) > > + > > /* Names of Hardware non-queue generic interrupts */ static char > > *cn93_non_ioq_msix_names[] =3D { > > "epf_ire_rint", > > @@ -199,6 +202,8 @@ static void octep_init_config_cn93_pf(struct > octep_device *oct) > > struct octep_config *conf =3D oct->conf; > > struct pci_dev *pdev =3D oct->pdev; > > u64 val; > > + int pos; > > + u8 link =3D 0; >=20 > RCT again >=20 Very sorry for missing these before submitting; Will take care next time. > > > > /* Read ring configuration: > > * PF ring count, number of VFs and rings per VF supported @@ - > 234,7 > > +239,16 @@ static void octep_init_config_cn93_pf(struct octep_device > *oct) > > conf->msix_cfg.ioq_msix =3D conf->pf_ring_cfg.active_io_rings; > > conf->msix_cfg.non_ioq_msix_names =3D > cn93_non_ioq_msix_names; > > > > - conf->ctrl_mbox_cfg.barmem_addr =3D (void __iomem *)oct- > >mmio[2].hw_addr + (0x400000ull * 7); > > + pos =3D pci_find_ext_capability(oct->pdev, PCI_EXT_CAP_ID_SRIOV); > > + if (pos) { > > + pci_read_config_byte(oct->pdev, > > + pos + PCI_SRIOV_FUNC_LINK, > > + &link); > > + link =3D PCI_DEVFN(PCI_SLOT(oct->pdev->devfn), link); > > + } > > + conf->ctrl_mbox_cfg.barmem_addr =3D (void __iomem *)oct- > >mmio[2].hw_addr + > > + (0x400000ull * 8) + >=20 > can you explain why s/7/8 and was it broken previously? >=20 Thank you for the feedback. Not broken; It works with 7. It was an experimental change only; should not have been included in the up= stream patch. Will revert this change in next revision. > > + (link * CTRL_MBOX_SZ); > > } > > > > /* Setup registers for a hardware Tx Queue */ > > -- > > 2.36.0 > >