Message-ID: <54238ab7-b7c0-a3a3-38e9-f7879866fb3c@schinagl.nl>
Date:   Sun, 19 Feb 2023 10:27:17 +0100
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Subject: Re: [PATCH] mips: Realtek RTL: select NO_EXCEPT_FILL
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To:     Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc:     Sander Vanheule <sander@svanheule.net>, linux-mips@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <20230115121922.6359-1-sander@svanheule.net>
 <20230127162755.GB6090@alpha.franken.de>
 <46724036-fabf-7bae-41f8-1e95c5f1db5c@schinagl.nl>
 <20230205161929.GD4459@alpha.franken.de>
 <f9c1be9c-478e-55e8-ad34-370641181015@schinagl.nl>
 <20230217173708.GA14134@alpha.franken.de>
 <af2cdad5-ee32-7956-cd77-2a18777a3857@schinagl.nl>
 <20230219090248.GE2924@alpha.franken.de>
From:   Olliver Schinagl <oliver@schinagl.nl>
In-Reply-To: <20230219090248.GE2924@alpha.franken.de>
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On 19-02-2023 10:02, Thomas Bogendoerfer wrote:
> On Fri, Feb 17, 2023 at 08:27:05PM +0100, Olliver Schinagl wrote:
>> It is the Realtek series of SoC, specifically in my case, the RTL9302b,
>> which doesn't have a PCI peripherial, at all :) Nor configured in the
>> devicetree, but of course generic_mips_kernel enables the drivers, which
>> should be noop. I don't see anything related to PCI during boot.
>>
>> Having said that, the RTL930x series take their heritage from the RTL819x
>> (and probably older) wifi SoC series from realtek, which did contain a PCIe
>> peripherial, as that is where the (external) wifi chip was connected too.
> I see, and you want to use the already existing wifi driver ?
Not at all, the rtl930x is a pure switch chip (10 serdes connecting to 
multiple PHY's yielding 24 - 48 (+ some SFP port) configurations, all 
without anything PCI related.
>
>>> Do you have a programmers manual for it,
>>> which contains details about the PCI bridge ?
>> If only. There are some (leaked) datasheets, that do contain the PCI
>> registers, mostly (obviously) the rtl819x datasheets. https://github.com/libc0607/Realtek_switch_hacking/blob/files/REALTEK-RTL8196E.pdf
>> is one such example that contains the PCIe registers.
> that's just the PCIe PHY part, but not the localbus<->PCIe bridge
> part. But if the wifi part of ypur SOC is directly connected to
> the localbus, having the some PCI register won't help anyway.
> I am afraid you need to go the route via extra Kconfig section.

It's still odd though; as we do not have _anything_ PCI, but it 
SWAP_IO_SPACE causes the crash.

So in that case, we'll wend up with a duplicate of generic_mips_kernel - 
SWAP_IO_SPACE, any suggestions of doing this cleanly in kconfig? copy 
pasting the whole shebang (and maintaining it) seems wasteful.

I suppose the chip is generic, except one thing makes it not generic :(


What makes SWAP_IO_SPACE generic then? :)

>
> Thomas.
>