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X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: t96Jo+R9OL67V6DHWSF2+VjQDFvKtyfSSGQe1In3glUsnJ8PpPAtsEhDu58mlpyS3a3OMrfOKoRpelGmOWIERsqoE+N28/OpfjktAna3Wj8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR03MB6322 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 20/02/2023 9:10 pm, Borislav Petkov wrote: > On Mon, Feb 20, 2023 at 07:57:25PM +0000, Andrew Cooper wrote: >> I think we're discussing the legacy IBRS case here.  i.e. what was >> retrofitted in microcode for existing parts? > Any IBRS actually. The one which is *not* the automatic, fire'n'forget > thing. /sigh so we're still talking about 3 different things then. 1) Intel's legacy IBRS 2) AMD's regular IBRS 3) AMD's AutoIBRS which all have different relevant behaviours for userspace.  Just so it's written out coherently in at least one place... When SEV-SNP is enabled in firmware, whether or not it's being used by software, AutoIBRS keeps indirect predictions inhibited in all of ASID0.  That's all host userspace to the non-hypervisor devs reading this thread. For any AMD configuration setting STIBP, there must be an IBPB after having set STIBP.   Setting STIBP alone does not evict previously created shared predictions.  This one can go subtly wrong for anyone who assumes that Intel STIBP and AMD STIBP have the same behaviour. Furthermore, extra care needs taking on vmexit because transitioning from the guest STIBP setting to the host STIBP setting can leave shared predictions intact. ~Andrew