Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D4AEC61DA3 for ; Tue, 21 Feb 2023 12:08:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234730AbjBUMIp (ORCPT ); Tue, 21 Feb 2023 07:08:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234722AbjBUMIk (ORCPT ); Tue, 21 Feb 2023 07:08:40 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4186B7682; Tue, 21 Feb 2023 04:08:10 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6nZG021211; Tue, 21 Feb 2023 06:06:49 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1676981209; bh=+kcDCV6HpKYD8UpyBRBFVFJIxT99SqqWM2VdYAPa2/4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=W+RUvCzQPoyhLoUee47wefBZQwcZm0g0SINCkemKbVcy3xjDUJMqtZutPBIWekRea hC/ZYKt5irQi193+jnWmS6nNE1IUrvcDumkhPAg1Bp4j7/T4XS2RSD01B9KsmrUNBw zWmJpPiPrgrmJy8hVxZXI9FF3+QCaYPvupb80vfQ= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 31LC6nqm045075 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 21 Feb 2023 06:06:49 -0600 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 21 Feb 2023 06:06:49 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 21 Feb 2023 06:06:49 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6CbW030829; Tue, 21 Feb 2023 06:06:45 -0600 From: Ravi Gunasekaran To: , , , , , , , CC: , , Subject: [PATCH v10 9/9] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe Date: Tue, 21 Feb 2023 17:36:12 +0530 Message-ID: <20230221120612.27366-10-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230221120612.27366-1-r-gunasekaran@ti.com> References: <20230221120612.27366-1-r-gunasekaran@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Aswath Govindraju x1 lane PCIe slot in the common processor board is enabled and connected to J721S2 SOM. Add PCIe DT node in common processor board to reflect the same. Reviewed-by: Siddharth Vadapalli Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Signed-off-by: Matt Ranostay Link: https://lore.kernel.org/r/20221122101616.770050-9-mranostay@ti.com Signed-off-by: Ravi Gunasekaran --- arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 76b420379645..b195f250891a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -386,6 +386,14 @@ }; }; +&pcie1_rc { + status = "okay"; + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; -- 2.17.1