Message-ID: <b90c582b8ddf0429058361ff42dc63ad1337bf43.camel@microchip.com>
Subject: Re: [PATCH v2 1/3] arm64: dts: microchip: sparx5: do not use PSCI
 on reference boards
From:   Steen Hegelund <steen.hegelund@microchip.com>
To:     Robert Marko <robert.marko@sartura.hr>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <lars.povlsen@microchip.com>,
        <daniel.machon@microchip.com>, <UNGLinuxDriver@microchip.com>,
        <arnd@arndb.de>, <alexandre.belloni@bootlin.com>,
        <devicetree@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>
CC:     <luka.perkov@sartura.hr>
Date:   Tue, 21 Feb 2023 14:59:56 +0100
In-Reply-To: <20230221105039.316819-1-robert.marko@sartura.hr>
References: <20230221105039.316819-1-robert.marko@sartura.hr>
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Hi Robert,

I find this very useful since the Sparx5 SoC does not support TFA and there=
fore
cannot provide PSCI on its own, as you also state below.

Acked-by: Steen Hegelund <Steen.Hegelund@microchip.com>

On Tue, 2023-02-21 at 11:50 +0100, Robert Marko wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know th=
e
> content is safe
>=20
> PSCI is not implemented on SparX-5 at all, there is no ATF and U-boot tha=
t
> is shipped does not implement it as well.
>=20
> I have tried flashing the latest BSP 2022.12 U-boot which did not work.
> After contacting Microchip, they confirmed that there is no ATF for the
> SoC nor PSCI implementation which is unfortunate in 2023.
>=20
> So, disable PSCI as otherwise kernel crashes as soon as it tries probing
> PSCI with, and the crash is only visible if earlycon is used.
>=20
> Since PSCI is not implemented, switch core bringup to use spin-tables
> which are implemented in the vendor U-boot and actually work.
>=20
> Tested on PCB134 with eMMC (VSC5640EV).
>=20
> Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support")
> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
> ---
> Changes in v2:
> * As suggested by Arnd, disable PSCI only on reference boards
> ---
> =C2=A0arch/arm64/boot/dts/microchip/sparx5.dtsi=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 2 +-
> =C2=A0arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi | 12 +++++++++=
+++
> =C2=A02 files changed, 13 insertions(+), 1 deletion(-)
>=20
> diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> index 0367a00a269b3..5eae6e7fd248e 100644
> --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
> +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
> @@ -61,7 +61,7 @@ arm-pmu {
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 interrupt-affinity =3D <&cpu0>, <&cpu1>;
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 };
>=20
> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 psci {
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 psci: psci {
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 compatible =3D "arm,psci-0.2";
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 method =3D "smc";
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 };
> diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
> b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
> index 9d1a082de3e29..32bb76b3202a0 100644
> --- a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
> +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
> @@ -6,6 +6,18 @@
> =C2=A0/dts-v1/;
> =C2=A0#include "sparx5.dtsi"
>=20
> +&psci {
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 status =3D "disabled";
> +};
> +
> +&cpu0 {
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 enable-method =3D "spin-table";
> +};
> +
> +&cpu1 {
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 enable-method =3D "spin-table";
> +};
> +
> =C2=A0&uart0 {
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 status =3D "okay";
> =C2=A0};
> --
> 2.39.2
>=20


BR
Steen