Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C71D5C636D7 for ; Tue, 21 Feb 2023 17:15:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233765AbjBURPU (ORCPT ); Tue, 21 Feb 2023 12:15:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234913AbjBURPQ (ORCPT ); Tue, 21 Feb 2023 12:15:16 -0500 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E973F1716D; Tue, 21 Feb 2023 09:15:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676999708; x=1708535708; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=QdJajH3RxhrYdlNw8KTJfiDzxCApfZOPL9kqRYCx/XQ=; b=A8/7LS9dmNPtZwI7QBblDS7NnT9ONVsrfnLtNWgVDf/MtBvZSNw8isV2 lTxJgRzvO0W4APDI0z5eb3AmXEysZ6fj6qURFB02jOxnxBw9b0YyWCatN 1kAL9C94AdsAVy1e/ai5ybBS01LuxjNAb9zcQplK8lZrCCMiObkWmgCkU 01KPp2oMneAfeXk79+2AYDk9uAP3UBg95XAC93JIRiPZCEJRV5KFockLs 7kD3XFe7SK/jxOVFO1fCmU0z00em9rvQdzG2SAGbqvbJKrEoi7bl7OmK+ 3YDWTJQobVfNAis9FHNvopsf+/RO9ziFpSXmKKy6ShSRx8b6ME/e1v3tj g==; X-IronPort-AV: E=McAfee;i="6500,9779,10628"; a="360169581" X-IronPort-AV: E=Sophos;i="5.97,315,1669104000"; d="scan'208";a="360169581" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Feb 2023 09:14:07 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10628"; a="735555441" X-IronPort-AV: E=Sophos;i="5.97,315,1669104000"; d="scan'208";a="735555441" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [10.213.184.163]) ([10.213.184.163]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Feb 2023 09:14:07 -0800 Message-ID: <5fc5d37d-e65a-10db-14c4-91f3a99fca91@intel.com> Date: Tue, 21 Feb 2023 10:14:06 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Firefox/102.0 Thunderbird/102.6.0 Subject: Re: [PATCH] cxl/hdm: dev_warn() on unsupported mixed mode decoder Content-Language: en-US To: alison.schofield@intel.com, Dan Williams , Ira Weiny , Vishal Verma , Ben Widawsky Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230218013834.31237-1-alison.schofield@intel.com> From: Dave Jiang In-Reply-To: <20230218013834.31237-1-alison.schofield@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2/17/23 6:38 PM, alison.schofield@intel.com wrote: > From: Alison Schofield > > A mixed mode decoder is programmed with device physical addresses > that span both ram and pmem partitions of a memdev. > > Linux does not support mixed mode decoders. The driver rejects > sysfs writes that try to set decoder mode to mixed, and if a > resource bieng allocated is not wholly contained in either the > pmem or ram partition of a memdev, it is also rejected. Basically, > the CXL region driver is not going to create regions with mixed > mode decoders, but the BIOS could. > > If the kernel driver sees the mixed mode decoder, it will fail to > enable the region, and emit a dev_dbg() message. > > A dev_dbg() is not noisy enough in this case. Change the message > to be a dev_warn() that explicitly says mixed mode is not supported. > > Suggested-by: Dan Williams > Signed-off-by: Alison Schofield Reviewed-by: Dave Jiang > --- > drivers/cxl/core/hdm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c > index 45deda18ed32..9eaf93c8ebb0 100644 > --- a/drivers/cxl/core/hdm.c > +++ b/drivers/cxl/core/hdm.c > @@ -294,8 +294,8 @@ static int __cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, > else if (resource_contains(&cxlds->ram_res, res)) > cxled->mode = CXL_DECODER_RAM; > else { > - dev_dbg(dev, "decoder%d.%d: %pr mixed\n", port->id, > - cxled->cxld.id, cxled->dpa_res); > + dev_warn(dev, "decoder%d.%d: %pr mixed mode not supported\n", > + port->id, cxled->cxld.id, cxled->dpa_res); > cxled->mode = CXL_DECODER_MIXED; > } > > > base-commit: a5fcd228ca1db9810ba1ed461c90b6ee933b9daf