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Date:   Tue, 21 Feb 2023 14:40:00 -0500
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To:     Rob Clark <robdclark@gmail.com>, dri-devel@lists.freedesktop.org
Cc:     freedreno@lists.freedesktop.org, Daniel Vetter <daniel@ffwll.ch>,
        =?UTF-8?Q?Christian_K=c3=b6nig?= <ckoenig.leichtzumerken@gmail.com>,
        =?UTF-8?Q?Michel_D=c3=a4nzer?= <michel@daenzer.net>,
        Tvrtko Ursulin <tvrtko.ursulin@intel.com>,
        Rodrigo Vivi <rodrigo.vivi@intel.com>,
        Alex Deucher <alexander.deucher@amd.com>,
        Pekka Paalanen <ppaalanen@gmail.com>,
        Simon Ser <contact@emersion.fr>,
        Rob Clark <robdclark@chromium.org>,
        David Airlie <airlied@gmail.com>,
        Sumit Semwal <sumit.semwal@linaro.org>,
        =?UTF-8?Q?Christian_K=c3=b6nig?= <christian.koenig@amd.com>,
        open list <linux-kernel@vger.kernel.org>,
        "open list:DMA BUFFER SHARING FRAMEWORK" 
        <linux-media@vger.kernel.org>,
        "moderated list:DMA BUFFER SHARING FRAMEWORK" 
        <linaro-mm-sig@lists.linaro.org>
References: <20230218211608.1630586-1-robdclark@gmail.com>
 <20230218211608.1630586-9-robdclark@gmail.com>
From:   Luben Tuikov <luben.tuikov@amd.com>
Subject: Re: [PATCH v4 08/14] drm/scheduler: Add fence deadline support
In-Reply-To: <20230218211608.1630586-9-robdclark@gmail.com>
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 =?utf-8?B?dmZTM1FqcG1FcmxFdkJ0TGs2OHk2aUZFVElBL25kc0VYamcxSEdTT25iQmtz?=
 =?utf-8?B?Qm1iTmFlWHl2eVpCaDBPUHMyUmVteWJLQ3pOMTc0UXBxbUpSM1cwczUySXVi?=
 =?utf-8?B?YlFCeW51WHp1YS9hK0FDY0xXS3Q0K0VENUFkeDA4Ly8zRlBBVDlqWmtjdS9s?=
 =?utf-8?B?NGNJa1VsdElvdDdTMER6bVV4UXpMWkw3YnI5eTU1QVorRXlKVXFlZGFtQUx0?=
 =?utf-8?B?YWI4NVp1U2IrM0NObG8xSnhkTnZxS3hJZ2pIdDJYOHpGOEJtdEE4REcvMTYr?=
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 =?utf-8?B?bkduQTkvT0pIdndmMU9zUWhpTmEyZWZhUmNpSjQ2SnYycS9CTU9DUFRRbjNk?=
 =?utf-8?B?dTc2UHJ6dUF4MFdweWp6RWd1Ky9zREtGTzcrRWpSZWVzWENCRW1FZjN5aDRP?=
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 =?utf-8?B?RHZWQVNkN3h5dWlHSFVTaGxwaXJyd3JVRS9PbWtIdnc1V2FnVDJ6YUNpYUR3?=
 =?utf-8?B?ODJJZCtWVmZUTkZhVy9XdXRCbnNnTUtwbmUvMDJuQ1hkTEwzdDhJbEh4WnZT?=
 =?utf-8?B?YkhvY0d6QUtJZkJnVUdwRmUvbFZXbVdTS0Z1YU5ZWkpTZStkNHk1a0NyKzd3?=
 =?utf-8?B?QWozb055QU9KblpCclVCZ2luZ3JhNTM2MGxVVkoraDhVQjJIeERQbm1oY2dF?=
 =?utf-8?B?NDJMRXB4WG9hSk1WYnRiak1yTWxwbmd4RTZDTkRKQ0FwRWNGSXh1NlJlREM0?=
 =?utf-8?B?Vk9mWGdaWEZQMlIvQ1I3NkdqOTU4em9yTVRTL0dvby9PRmgza096NVF5cGtQ?=
 =?utf-8?B?VHJrZC8yK2JkSWJUcUh0VkVrc2RENzAwRFZwVzlaSjNFcm9wa3E2YnlaSFkz?=
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 =?utf-8?B?VmtGaGVybkQ4UlBYcEJ2K0ZCRTRsVGUrUUI3ck9qdzVJK3BVaTJqTjRhNk8z?=
 =?utf-8?Q?eJUPXnmemCAW45gsZ1NZTrfKe?=
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On 2023-02-18 16:15, Rob Clark wrote:
> As the finished fence is the one that is exposed to userspace, and
> therefore the one that other operations, like atomic update, would
> block on, we need to propagate the deadline from from the finished
> fence to the actual hw fence.
> 
> v2: Split into drm_sched_fence_set_parent() (ckoenig)
> v3: Ensure a thread calling drm_sched_fence_set_deadline_finished() sees
>     fence->parent set before drm_sched_fence_set_parent() does this
>     test_bit(DMA_FENCE_FLAG_HAS_DEADLINE_BIT).
> 
> Signed-off-by: Rob Clark <robdclark@chromium.org>

Looks good.

This patch is Acked-by: Luben Tuikov <luben.tuikov@amd.com>
-- 
Regards,
Luben

> ---
>  drivers/gpu/drm/scheduler/sched_fence.c | 46 +++++++++++++++++++++++++
>  drivers/gpu/drm/scheduler/sched_main.c  |  2 +-
>  include/drm/gpu_scheduler.h             |  8 +++++
>  3 files changed, 55 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/scheduler/sched_fence.c b/drivers/gpu/drm/scheduler/sched_fence.c
> index 7fd869520ef2..43e2d4f5fe3b 100644
> --- a/drivers/gpu/drm/scheduler/sched_fence.c
> +++ b/drivers/gpu/drm/scheduler/sched_fence.c
> @@ -123,6 +123,37 @@ static void drm_sched_fence_release_finished(struct dma_fence *f)
>  	dma_fence_put(&fence->scheduled);
>  }
>  
> +static void drm_sched_fence_set_deadline_finished(struct dma_fence *f,
> +						  ktime_t deadline)
> +{
> +	struct drm_sched_fence *fence = to_drm_sched_fence(f);
> +	struct dma_fence *parent;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&fence->lock, flags);
> +
> +	/* If we already have an earlier deadline, keep it: */
> +	if (test_bit(DMA_FENCE_FLAG_HAS_DEADLINE_BIT, &f->flags) &&
> +	    ktime_before(fence->deadline, deadline)) {
> +		spin_unlock_irqrestore(&fence->lock, flags);
> +		return;
> +	}
> +
> +	fence->deadline = deadline;
> +	set_bit(DMA_FENCE_FLAG_HAS_DEADLINE_BIT, &f->flags);
> +
> +	spin_unlock_irqrestore(&fence->lock, flags);
> +
> +	/*
> +	 * smp_load_aquire() to ensure that if we are racing another
> +	 * thread calling drm_sched_fence_set_parent(), that we see
> +	 * the parent set before it calls test_bit(HAS_DEADLINE_BIT)
> +	 */
> +	parent = smp_load_acquire(&fence->parent);
> +	if (parent)
> +		dma_fence_set_deadline(parent, deadline);
> +}
> +
>  static const struct dma_fence_ops drm_sched_fence_ops_scheduled = {
>  	.get_driver_name = drm_sched_fence_get_driver_name,
>  	.get_timeline_name = drm_sched_fence_get_timeline_name,
> @@ -133,6 +164,7 @@ static const struct dma_fence_ops drm_sched_fence_ops_finished = {
>  	.get_driver_name = drm_sched_fence_get_driver_name,
>  	.get_timeline_name = drm_sched_fence_get_timeline_name,
>  	.release = drm_sched_fence_release_finished,
> +	.set_deadline = drm_sched_fence_set_deadline_finished,
>  };
>  
>  struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f)
> @@ -147,6 +179,20 @@ struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f)
>  }
>  EXPORT_SYMBOL(to_drm_sched_fence);
>  
> +void drm_sched_fence_set_parent(struct drm_sched_fence *s_fence,
> +				struct dma_fence *fence)
> +{
> +	/*
> +	 * smp_store_release() to ensure another thread racing us
> +	 * in drm_sched_fence_set_deadline_finished() sees the
> +	 * fence's parent set before test_bit()
> +	 */
> +	smp_store_release(&s_fence->parent, dma_fence_get(fence));
> +	if (test_bit(DMA_FENCE_FLAG_HAS_DEADLINE_BIT,
> +		     &s_fence->finished.flags))
> +		dma_fence_set_deadline(fence, s_fence->deadline);
> +}
> +
>  struct drm_sched_fence *drm_sched_fence_alloc(struct drm_sched_entity *entity,
>  					      void *owner)
>  {
> diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c
> index 4e6ad6e122bc..007f98c48f8d 100644
> --- a/drivers/gpu/drm/scheduler/sched_main.c
> +++ b/drivers/gpu/drm/scheduler/sched_main.c
> @@ -1019,7 +1019,7 @@ static int drm_sched_main(void *param)
>  		drm_sched_fence_scheduled(s_fence);
>  
>  		if (!IS_ERR_OR_NULL(fence)) {
> -			s_fence->parent = dma_fence_get(fence);
> +			drm_sched_fence_set_parent(s_fence, fence);
>  			/* Drop for original kref_init of the fence */
>  			dma_fence_put(fence);
>  
> diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
> index 9db9e5e504ee..8b31a954a44d 100644
> --- a/include/drm/gpu_scheduler.h
> +++ b/include/drm/gpu_scheduler.h
> @@ -280,6 +280,12 @@ struct drm_sched_fence {
>           */
>  	struct dma_fence		finished;
>  
> +	/**
> +	 * @deadline: deadline set on &drm_sched_fence.finished which
> +	 * potentially needs to be propagated to &drm_sched_fence.parent
> +	 */
> +	ktime_t				deadline;
> +
>          /**
>           * @parent: the fence returned by &drm_sched_backend_ops.run_job
>           * when scheduling the job on hardware. We signal the
> @@ -568,6 +574,8 @@ void drm_sched_entity_set_priority(struct drm_sched_entity *entity,
>  				   enum drm_sched_priority priority);
>  bool drm_sched_entity_is_ready(struct drm_sched_entity *entity);
>  
> +void drm_sched_fence_set_parent(struct drm_sched_fence *s_fence,
> +				struct dma_fence *fence);
>  struct drm_sched_fence *drm_sched_fence_alloc(
>  	struct drm_sched_entity *s_entity, void *owner);
>  void drm_sched_fence_init(struct drm_sched_fence *fence,