Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CC06C636D7 for ; Wed, 22 Feb 2023 01:14:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230079AbjBVBOM (ORCPT ); Tue, 21 Feb 2023 20:14:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229609AbjBVBOK (ORCPT ); Tue, 21 Feb 2023 20:14:10 -0500 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0B9A4166CD for ; Tue, 21 Feb 2023 17:14:08 -0800 (PST) Received: from [192.168.87.25] (unknown [50.35.78.176]) by linux.microsoft.com (Postfix) with ESMTPSA id 33E7320B9C3D; Tue, 21 Feb 2023 17:14:07 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 33E7320B9C3D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1677028447; bh=YTkfcoTrsyGUhPbAsJNW1hFtxJhcxATFUQJzQJ+E840=; h=Date:Subject:To:References:From:In-Reply-To:From; b=ksjWfUD7hL4lluKkN4pyotZAcfERPzfs3CXBvbcHi0Lo+wPjs33I5/pVstNjH2kls q0vfgIXT9nM0kXJiEpsfRXOeOPz9TtJ1UY3OuEK7kN2aV/k9BZrA2waNzRTCKhOztW 1fe+pTK6b/qVT5wvs7gFyCbTFooPdzbctJdO2q/g= Message-ID: Date: Tue, 21 Feb 2023 17:14:07 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v5 1/2] dt-bindings: i2c: Add support for ASPEED i2Cv2 Content-Language: en-US To: Ryan Chen , Jeremy Kerr , Rob Herring , Krzysztof Kozlowski , Joel Stanley , Andrew Jeffery , Philipp Zabel , "openbmc@lists.ozlabs.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" References: <20230220061745.1973981-1-ryan_chen@aspeedtech.com> <20230220061745.1973981-2-ryan_chen@aspeedtech.com> <2141e513acc750bf26775f5b435f4dccd41244aa.camel@codeconstruct.com.au> From: Dhananjay Phadke In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2/20/2023 7:32 PM, Ryan Chen wrote: >>>>> +  timeout: >>>>> +    type: boolean >>>>> +    description: Enable i2c bus timeout for master/slave (35ms) >>>>> + >>>>> +  byte-mode: >>>>> +    type: boolean >>>>> +    description: Force i2c driver use byte mode transmit >>>>> + >>>>> +  buff-mode: >>>>> +    type: boolean >>>>> +    description: Force i2c driver use buffer mode transmit >>>> >>>> These three aren't really a property of the hardware, more of the >>>> intended driver configuration. Do they really belong in the DT? >>>> >>> Sorry, I am confused. >>> This is hardware controller mode setting for each i2c transfer. >>> So I add it in property for change different i2c transfer mode. >>> Is my mis-understand the property setting? >> >> It depends what this is configuration is for. >> >> Would you set the transfer mode based on the design of the board? Is there >> something about the physical i2c bus wiring (or some other hardware design >> choice) that would mean you use one setting over another? >> > No, it not depend on board design. It is only for register control for controller transfer behave. > The controller support 3 different trigger mode for transfer. > Byte mode: it means step by step to issue transfer. > Example i2c read, each step will issue interrupt then driver need trigger for next step. > Sr (start read) | D | D | D | P > Buffer mode: it means, the data can prepare into buffer register, then Trigger transfer. So Sr D D D P, only have only 1 interrupt handling. > The DMA mode most like with buffer mode, The differ is data prepare in DRAM, than trigger transfer. > > Unless these settings like xfer mode are per i2c bus, it could be just a module parameter? Not sure anything other than default mode would be used if DMA mode works for all master/slave transactions. Regards, Dhananjay