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[93.5.22.158]) by smtp.gmail.com with ESMTPSA id c23-20020a05600c149700b003e2066a6339sm4550452wmh.5.2023.02.22.00.17.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Feb 2023 00:17:41 -0800 (PST) Message-ID: <8c348b39-67f3-9210-1929-8b2f093be24c@baylibre.com> Date: Wed, 22 Feb 2023 09:17:39 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH v9 9/9] arm64: dts: mediatek: Initial mt8365-evk support To: =?UTF-8?Q?Bernhard_Rosenkr=c3=a4nzer?= , linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tglx@linutronix.de, maz@kernel.org, lee@kernel.org, linus.walleij@linaro.org, matthias.bgg@gmail.com, gregkh@linuxfoundation.org, daniel.lezcano@linaro.org, chunfeng.yun@mediatek.com, angelogioacchino.delregno@collabora.com, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, sean.wang@mediatek.com, zhiyong.tao@mediatek.com, khilman@baylibre.com References: <20230125143503.1015424-1-bero@baylibre.com> <20230125143503.1015424-10-bero@baylibre.com> Content-Language: en-US From: Alexandre Mergnat In-Reply-To: <20230125143503.1015424-10-bero@baylibre.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Matthias, This is a gentle ping to know if you can take this patch please. Sorry for the double mail, I screwed up the first send. Best regards, Alex On 25/01/2023 15:35, Bernhard Rosenkränzer wrote: > From: Fabien Parent > > This adds minimal support for the Mediatek 8365 SOC and the EVK reference > board, allowing the board to boot to initramfs with serial port I/O. > > Signed-off-by: Fabien Parent > [bero@baylibre.com: Removed parts depending on drivers that aren't upstream yet, cleanups, add CPU cache layout, add systimer, fix GIC] > Signed-off-by: Bernhard Rosenkränzer > Tested-by: Kevin Hilman > Reviewed-by: AngeloGioacchino Del Regno > --- > arch/arm64/boot/dts/mediatek/Makefile | 1 + > arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 168 +++++++++ > arch/arm64/boot/dts/mediatek/mt8365.dtsi | 377 ++++++++++++++++++++ > 3 files changed, 546 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > index 813e735c5b96d..d78523c5a7dd6 100644 > --- a/arch/arm64/boot/dts/mediatek/Makefile > +++ b/arch/arm64/boot/dts/mediatek/Makefile > @@ -47,4 +47,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb > diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts > new file mode 100644 > index 0000000000000..4683704ea2355 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts > @@ -0,0 +1,168 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2021-2022 BayLibre, SAS. > + * Authors: > + * Fabien Parent > + * Bernhard Rosenkränzer > + */ > + > +/dts-v1/; > + > +#include > +#include > +#include > +#include "mt8365.dtsi" > + > +/ { > + model = "MediaTek MT8365 Open Platform EVK"; > + compatible = "mediatek,mt8365-evk", "mediatek,mt8365"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:921600n8"; > + }; > + > + firmware { > + optee { > + compatible = "linaro,optee-tz"; > + method = "smc"; > + }; > + }; > + > + gpio-keys { > + compatible = "gpio-keys"; > + pinctrl-names = "default"; > + pinctrl-0 = <&gpio_keys>; > + > + key-volume-up { > + gpios = <&pio 24 GPIO_ACTIVE_LOW>; > + label = "volume_up"; > + linux,code = ; > + wakeup-source; > + debounce-interval = <15>; > + }; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0 0x40000000 0 0xc0000000>; > + }; > + > + usb_otg_vbus: regulator-0 { > + compatible = "regulator-fixed"; > + regulator-name = "otg_vbus"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&pio 16 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ > + bl31_secmon_reserved: secmon@43000000 { > + no-map; > + reg = <0 0x43000000 0 0x20000>; > + }; > + > + /* 12 MiB reserved for OP-TEE (BL32) > + * +-----------------------+ 0x43e0_0000 > + * | SHMEM 2MiB | > + * +-----------------------+ 0x43c0_0000 > + * | | TA_RAM 8MiB | > + * + TZDRAM +--------------+ 0x4340_0000 > + * | | TEE_RAM 2MiB | > + * +-----------------------+ 0x4320_0000 > + */ > + optee_reserved: optee@43200000 { > + no-map; > + reg = <0 0x43200000 0 0x00c00000>; > + }; > + }; > +}; > + > +&pio { > + gpio_keys: gpio-keys-pins { > + pins { > + pinmux = ; > + bias-pull-up; > + input-enable; > + }; > + }; > + > + uart0_pins: uart0-pins { > + pins { > + pinmux = , > + ; > + }; > + }; > + > + uart1_pins: uart1-pins { > + pins { > + pinmux = , > + ; > + }; > + }; > + > + uart2_pins: uart2-pins { > + pins { > + pinmux = , > + ; > + }; > + }; > + > + usb_pins: usb-pins { > + id-pins { > + pinmux = ; > + input-enable; > + bias-pull-up; > + }; > + > + usb0-vbus-pins { > + pinmux = ; > + output-high; > + }; > + > + usb1-vbus-pins { > + pinmux = ; > + output-high; > + }; > + }; > + > + pwm_pins: pwm-pins { > + pins { > + pinmux = , > + ; > + }; > + }; > +}; > + > +&pwm { > + pinctrl-0 = <&pwm_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&uart0 { > + pinctrl-0 = <&uart0_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&uart1 { > + pinctrl-0 = <&uart1_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&uart2 { > + pinctrl-0 = <&uart2_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi > new file mode 100644 > index 0000000000000..15ac4c1f09661 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi > @@ -0,0 +1,377 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * (C) 2018 MediaTek Inc. > + * Copyright (C) 2022 BayLibre SAS > + * Fabien Parent > + * Bernhard Rosenkränzer > + */ > +#include > +#include > +#include > +#include > + > +/ { > + compatible = "mediatek,mt8365"; > + interrupt-parent = <&sysirq>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x0>; > + #cooling-cells = <2>; > + enable-method = "psci"; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x1>; > + #cooling-cells = <2>; > + enable-method = "psci"; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2>; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x2>; > + #cooling-cells = <2>; > + enable-method = "psci"; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2>; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x3>; > + #cooling-cells = <2>; > + enable-method = "psci"; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2>; > + }; > + > + l2: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-size = <0x80000>; > + cache-line-size = <64>; > + cache-sets = <512>; > + cache-unified; > + }; > + }; > + > + clk26m: oscillator { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <26000000>; > + clock-output-names = "clk26m"; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + ranges; > + > + gic: interrupt-controller@c000000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + reg = <0 0x0c000000 0 0x10000>, /* GICD */ > + <0 0x0c080000 0 0x80000>, /* GICR */ > + <0 0x0c400000 0 0x2000>, /* GICC */ > + <0 0x0c410000 0 0x1000>, /* GICH */ > + <0 0x0c420000 0 0x2000>; /* GICV */ > + > + interrupts = ; > + }; > + > + topckgen: syscon@10000000 { > + compatible = "mediatek,mt8365-topckgen", "syscon"; > + reg = <0 0x10000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + infracfg: syscon@10001000 { > + compatible = "mediatek,mt8365-infracfg", "syscon"; > + reg = <0 0x10001000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + pericfg: syscon@10003000 { > + compatible = "mediatek,mt8365-pericfg", "syscon"; > + reg = <0 0x10003000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + syscfg_pctl: syscfg-pctl@10005000 { > + compatible = "mediatek,mt8365-syscfg", "syscon"; > + reg = <0 0x10005000 0 0x1000>; > + }; > + > + pio: pinctrl@1000b000 { > + compatible = "mediatek,mt8365-pinctrl"; > + reg = <0 0x1000b000 0 0x1000>; > + mediatek,pctl-regmap = <&syscfg_pctl>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = ; > + }; > + > + apmixedsys: syscon@1000c000 { > + compatible = "mediatek,mt8365-apmixedsys", "syscon"; > + reg = <0 0x1000c000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + keypad: keypad@10010000 { > + compatible = "mediatek,mt6779-keypad"; > + reg = <0 0x10010000 0 0x1000>; > + wakeup-source; > + interrupts = ; > + clocks = <&clk26m>; > + clock-names = "kpd"; > + status = "disabled"; > + }; > + > + mcucfg: syscon@10200000 { > + compatible = "mediatek,mt8365-mcucfg", "syscon"; > + reg = <0 0x10200000 0 0x2000>; > + #clock-cells = <1>; > + }; > + > + sysirq: interrupt-controller@10200a80 { > + compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupt-parent = <&gic>; > + reg = <0 0x10200a80 0 0x20>; > + }; > + > + infracfg_nao: infracfg@1020e000 { > + compatible = "mediatek,mt8365-infracfg", "syscon"; > + reg = <0 0x1020e000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + rng: rng@1020f000 { > + compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; > + reg = <0 0x1020f000 0 0x100>; > + clocks = <&infracfg CLK_IFR_TRNG>; > + clock-names = "rng"; > + }; > + > + apdma: dma-controller@11000280 { > + compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; > + reg = <0 0x11000280 0 0x80>, > + <0 0x11000300 0 0x80>, > + <0 0x11000380 0 0x80>, > + <0 0x11000400 0 0x80>, > + <0 0x11000580 0 0x80>, > + <0 0x11000600 0 0x80>; > + interrupts = , > + , > + , > + , > + , > + ; > + dma-requests = <6>; > + clocks = <&infracfg CLK_IFR_AP_DMA>; > + clock-names = "apdma"; > + #dma-cells = <1>; > + }; > + > + uart0: serial@11002000 { > + compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; > + reg = <0 0x11002000 0 0x1000>; > + interrupts = ; > + clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; > + clock-names = "baud", "bus"; > + dmas = <&apdma 0>, <&apdma 1>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + uart1: serial@11003000 { > + compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; > + reg = <0 0x11003000 0 0x1000>; > + interrupts = ; > + clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; > + clock-names = "baud", "bus"; > + dmas = <&apdma 2>, <&apdma 3>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + uart2: serial@11004000 { > + compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; > + reg = <0 0x11004000 0 0x1000>; > + interrupts = ; > + clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; > + clock-names = "baud", "bus"; > + dmas = <&apdma 4>, <&apdma 5>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + pwm: pwm@11006000 { > + compatible = "mediatek,mt8365-pwm"; > + reg = <0 0x11006000 0 0x1000>; > + #pwm-cells = <2>; > + interrupts = ; > + clocks = <&infracfg CLK_IFR_PWM_HCLK>, > + <&infracfg CLK_IFR_PWM>, > + <&infracfg CLK_IFR_PWM1>, > + <&infracfg CLK_IFR_PWM2>, > + <&infracfg CLK_IFR_PWM3>; > + clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; > + }; > + > + spi: spi@1100a000 { > + compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; > + reg = <0 0x1100a000 0 0x100>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, > + <&topckgen CLK_TOP_SPI_SEL>, > + <&infracfg CLK_IFR_SPI0>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + status = "disabled"; > + }; > + > + ssusb: usb@11201000 { > + compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; > + reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; > + reg-names = "mac", "ippc"; > + interrupts = ; > + phys = <&u2port0 PHY_TYPE_USB2>, > + <&u2port1 PHY_TYPE_USB2>; > + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, > + <&infracfg CLK_IFR_SSUSB_REF>, > + <&infracfg CLK_IFR_SSUSB_SYS>, > + <&infracfg CLK_IFR_ICUSB>; > + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; > + > + usb_host: usb@11200000 { > + compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; > + reg = <0 0x11200000 0 0x1000>; > + reg-names = "mac"; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, > + <&infracfg CLK_IFR_SSUSB_REF>, > + <&infracfg CLK_IFR_SSUSB_SYS>, > + <&infracfg CLK_IFR_ICUSB>, > + <&infracfg CLK_IFR_SSUSB_XHCI>; > + clock-names = "sys_ck", "ref_ck", "mcu_ck", > + "dma_ck", "xhci_ck"; > + status = "disabled"; > + }; > + }; > + > + u3phy: t-phy@11cc0000 { > + compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0x11cc0000 0x9000>; > + > + u2port0: usb-phy@0 { > + reg = <0x0 0x400>; > + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, > + <&topckgen CLK_TOP_USB20_48M_EN>; > + clock-names = "ref", "da_ref"; > + #phy-cells = <1>; > + }; > + > + u2port1: usb-phy@1000 { > + reg = <0x1000 0x400>; > + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, > + <&topckgen CLK_TOP_USB20_48M_EN>; > + clock-names = "ref", "da_ref"; > + #phy-cells = <1>; > + }; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupt-parent = <&gic>; > + interrupts = , > + , > + , > + ; > + }; > + > + system_clk: dummy13m { > + compatible = "fixed-clock"; > + clock-frequency = <13000000>; > + #clock-cells = <0>; > + }; > + > + systimer: timer@10017000 { > + compatible = "mediatek,mt8365-systimer", "mediatek,mt6795-systimer"; > + reg = <0 0x10017000 0 0x10>; > + interrupts = ; > + clocks = <&system_clk>; > + clock-names = "clk13m"; > + }; > +};