Message-ID: <25c01857-8f59-02ed-062d-a5e619258204@starfivetech.com>
Date:   Thu, 23 Feb 2023 11:40:40 +0800
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Subject: Re: [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system
 clock and reset generator
Content-Language: en-US
To:     Conor Dooley <conor@kernel.org>
CC:     <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-riscv@lists.infradead.org>, Stephen Boyd <sboyd@kernel.org>,
        "Michael Turquette" <mturquette@baylibre.com>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Ben Dooks <ben.dooks@sifive.com>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        "Emil Renner Berthing" <emil.renner.berthing@canonical.com>,
        <linux-kernel@vger.kernel.org>
References: <20230221024645.127922-1-hal.feng@starfivetech.com>
 <20230221024645.127922-10-hal.feng@starfivetech.com> <Y/T+GNQAXLGyUtCH@spud>
From:   Hal Feng <hal.feng@starfivetech.com>
In-Reply-To: <Y/T+GNQAXLGyUtCH@spud>
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On Tue, 21 Feb 2023 17:23:36 +0000, Conor Dooley wrote:
> Hey Hal,
> 
> On Tue, Feb 21, 2023 at 10:46:35AM +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>> 
>> Add bindings for the system clock and reset generator (SYSCRG) on the
>> JH7110 RISC-V SoC by StarFive Ltd.
>> 
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> 
>> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
>> new file mode 100644
>> index 000000000000..ec81504dcb27
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
>> @@ -0,0 +1,80 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 System Clock and Reset Generator
>> +
>> +maintainers:
>> +  - Emil Renner Berthing <kernel@esmil.dk>
>> +
>> +properties:
>> +  compatible:
>> +    const: starfive,jh7110-syscrg
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  clocks:
>> +    items:
>> +      - description: Main Oscillator (24 MHz)
>> +      - description: GMAC1 RMII reference
>> +      - description: GMAC1 RGMII RX
>> +      - description: External I2S TX bit clock
>> +      - description: External I2S TX left/right channel clock
>> +      - description: External I2S RX bit clock
>> +      - description: External I2S RX left/right channel clock
>> +      - description: External TDM clock
>> +      - description: External audio master clock
> 
> You didn't reply to the conversation I had with Krzysztof about how to
> represent the optional nature of some of these clocks, contained in this
> thread here:
> https://lore.kernel.org/all/7a7bccb1-4d47-3d32-36e6-4aab7b5b8dad@starfivetech.com/
> 
> What happens to the gmac1 mux if only one of the input clocks is
> provided?
> And I mean what does the hardware do, not the software representation of
> that mux in the driver.

In hardware, just providing the required input clocks is enough. Refer to the
following link for the required clocks. Thanks.

https://lore.kernel.org/all/c0472d7f-56fe-3e91-e0a0-49ee51700b5d@starfivetech.com/

Best regards,
Hal

> 
>> +
>> +  clock-names:
>> +    items:
>> +      - const: osc
>> +      - const: gmac1_rmii_refin
>> +      - const: gmac1_rgmii_rxin
>> +      - const: i2stx_bclk_ext
>> +      - const: i2stx_lrck_ext
>> +      - const: i2srx_bclk_ext
>> +      - const: i2srx_lrck_ext
>> +      - const: tdm_ext
>> +      - const: mclk_ext