Date:   Thu, 23 Feb 2023 10:13:54 +0530
From:   Kautuk Consul <kconsul@linux.vnet.ibm.com>
To:     Michael Ellerman <mpe@ellerman.id.au>
Cc:     paulmck@kernel.org, Nicholas Piggin <npiggin@gmail.com>,
        Christophe Leroy <christophe.leroy@csgroup.eu>,
        Rohan McLure <rmclure@linux.ibm.com>,
        linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] arch/powerpc/include/asm/barrier.h: redefine rmb and
 wmb to  lwsync
Message-ID: <Y/bvClrV60CXK79G@li-a450e7cc-27df-11b2-a85c-b5a9ac31e8ef.ibm.com>
References: <20230222090344.189270-1-kconsul@linux.vnet.ibm.com>
 <20230222174719.GA1400185@paulmck-ThinkPad-P17-Gen-1>
 <87fsaxavk2.fsf@mpe.ellerman.id.au>
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Precedence: bulk

 
> You are correct, the patch is wrong because it fails to account for IO
> accesses.

Okay, I looked at the PowerPC ISA and found:
"The memory barrier provides an ordering function for the storage accesses
caused by Load, Store,and dcbz instructions that are executed by the processor
executing the sync instruction and for which the specified storage location
is in storage that is Memory Coherence Required and is neitherWrite Through
Required nor Caching Inhibited.The applicable pairs are all pairs ai ,bj of
such accesses except those in which ai is an accesscaused by a Store or dcbz
instruction and bj is anaccess caused by a Load instruction."

Thanks for your time, Michael. Sorry for the noise.
> 
> Kautuk, I'm not sure what motivated you to look at these barriers, was
> it just the documentation you linked to?
I read the basic documentation. Now that I have access to the PowerISA
document I guess I'll go through it more thoroughly.
>