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Thu, 23 Feb 2023 08:26:57 -0800 From: Krishna Yarlagadda To: , , , , , , , , , CC: , , , , Krishna Yarlagadda Subject: [Patch V3 2/3] spi: tegra210-quad: set half duplex flag Date: Thu, 23 Feb 2023 21:56:34 +0530 Message-ID: <20230223162635.19747-3-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230223162635.19747-1-kyarlagadda@nvidia.com> References: <20230223162635.19747-1-kyarlagadda@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT059:EE_|CH3PR12MB8305:EE_ X-MS-Office365-Filtering-Correlation-Id: 09bdbb92-7e9f-4840-21fb-08db15bad1dc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9fgk6S4g0Z+TIj2G5f/Bs53YdA0jUIyZ5rzZgkpd+JtdykgCNmkdSqSvT4LG08PZjTYD/TYNFKtk5vYHTJ/txQ0GK7MOcodAd9uWjPs6mU3OgtlaR6426ggc/bOdsL+nPuyeewH3oKHIJtK83MwhSsttPkZm7UTnJvs9CahdUO+AVmUvn+FUuxhD8GwFpTz99RsPqUWdwcCaq5iryOBMhQogvDVZVUvF1xvanpEUUj8bssaelv8ErEEQi+NLlDNPQiq/V+rA/iCC2Egnu7ScNYGj0pw7GMnb8i1Vuwu7NoE3dw4C6f/FscD8KEaP+VV+Yo1miK2hyWi86D5hZhwOq5rh2F5YlPPItBflz3nFuF4pCm9BUZduYBVxtm5xRO6/HnqH4gPKeuxqVZqDMEuouPBSfyjIiOhDxGVxcznTkzSdhL5dGLeJB23/gjFJlcVaX5/Fyt+Av8p2fRciy0n665GP+vugLWIHUJzbK3mJuUFkcyRyjvvlG5Mcwkg90hdEFeVndP7WyTdYtked7+oTULt+gfQJMBtlMEj+X5nWNzq7W+9+JOaUwNS4mCPWAhnTS2lKbOUBS5oZj1UcNh/oBPQbrq6a/NFvpYw1Ps9L/XonRGeknSascTamQyGmjMsYYYOO9C9/UA9NSwgp/ORPYn9piLGgl/aF7Dg8Nm0lTOMu7ta/UPANN2vj9D1owkvO230fC45Qz0+5Dq5l3WttglQqJxZc9ZFenQT8y9zLl9hH32hdrVVH753sTT259vg9gtCBmBElS+td+AwwVF49s4WgeDnmtqCjpIAwGT+1JfeCIi0vB++qYsyFi3T4LH3AvrPdNQU3l2GzrRSzoMkvmA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(396003)(39860400002)(346002)(136003)(376002)(451199018)(5400799012)(36840700001)(46966006)(40470700004)(2906002)(36756003)(82740400003)(316002)(336012)(107886003)(6666004)(7696005)(34020700004)(36860700001)(41300700001)(2616005)(426003)(7636003)(70206006)(1076003)(47076005)(40480700001)(70586007)(40460700003)(921005)(82310400005)(5660300002)(478600001)(83380400001)(54906003)(8676002)(110136005)(4326008)(4744005)(356005)(8936002)(26005)(186003)(7416002)(86362001)(83996005)(2101003)(12100799015);DIR:OUT;SFP:1501; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2023 16:27:12.9991 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 09bdbb92-7e9f-4840-21fb-08db15bad1dc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8305 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tegra QSPI controller only supports half duplex transfers. Set half duplex constrain flag. Signed-off-by: Krishna Yarlagadda --- drivers/spi/spi-tegra210-quad.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 9ddb02fc6f1b..b967576b6c96 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1532,6 +1532,7 @@ static int tegra_qspi_probe(struct platform_device *pdev) master->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_CS_HIGH | SPI_TX_DUAL | SPI_RX_DUAL | SPI_TX_QUAD | SPI_RX_QUAD; master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | SPI_BPW_MASK(8); + master->flags = SPI_CONTROLLER_HALF_DUPLEX; master->setup = tegra_qspi_setup; master->transfer_one_message = tegra_qspi_transfer_one_message; master->num_chipselect = 1; -- 2.17.1